// Copyright (c) 2024，D-Robotics.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

/***************************************************************************
* COPYRIGHT NOTICE
* Copyright 2019 Horizon Robotics, Inc.
* All rights reserved.
***************************************************************************/
#ifndef UTILITY_SENSOR_INC_OVX3C_SETTING_H_
#define UTILITY_SENSOR_INC_OVX3C_SETTING_H_

#define OVX3C_HCG_LCG_CG_RATIO  7.2
#define OVX3C_SENS_RATIO        113
#define OVX3C_HCG_LCG_RATIO     64
#define OVX3C_LCG_SPD_RATIO     2
#define OVX3C_LCG_VS_RATIO      64

#define OVX3C_LCG_SPD_RATIO_SN60     64
#define OVX3C_LCG_VS_RATIO_SN60      2

#define OVX3C_HCG_LCG_RATIO_OF  4
#define OVX3C_LCG_SPD_RATIO_OF  64

#define OVX3C_LCG_SPD_RATIO_LCE100   64
#define OVX3C_LCG_VS_RATIO_LCE100    2

#define OVX3C_COMMON_ADDR       0x10
//#define DCG_ADD_VS_LINE_MAX     678    //  vts - 12
#define VS_LINE_MAX             32
#define VS_LINE_MIN             0       //  actual 0.5row
#define DCG_LINE_MIN            10
#define DCG_LINE_MIN_GALAXY     16
#define SPD_LINE_MIN            1
#define LCG_VS_AGAIN_MIN        1
#define LCG_VS_DGAIN_MIN        1
#define HCG_AGAIN_MIN           1
#define SPD_AGAIN_MIN           4.25
#define AGAIN_MAX               15.5
#define DGAIN_MAX               15.999
#define DGAIN_MIN               1

#define D65_TEMPER              6500
#define CWF_TEMPER              4150
#define ALIGHT_TEMPER           2856

#define ALIGHT_LPD_BGAIN        3.34
#define ALIGHT_LPD_RGAIN        1.00
#define ALIGHT_LPD_GGAIN        1.05
#define ALIGHT_SPD_BGAIN        2.82
#define ALIGHT_SPD_RGAIN        1.00
#define ALIGHT_SPD_GGAIN        1.08
#define CWF_LPD_BGAIN           2.53
#define CWF_LPD_RGAIN           1.84
#define CWF_SPD_BGAIN           2.52
#define CWF_SPD_RGAIN           1.63
#define D65_LPD_BGAIN           1.49
#define D65_LPD_RGAIN           1.81
#define D65_SPD_BGAIN           1.59
#define D65_SPD_RGAIN           1.59

#define SN60_ALIGHT_LPD_BGAIN        3.34
#define SN60_ALIGHT_LPD_RGAIN        1.00
#define SN60_ALIGHT_LPD_GGAIN        1.05
#define SN60_ALIGHT_SPD_BGAIN        2.82
#define SN60_ALIGHT_SPD_RGAIN        1.00
#define SN60_ALIGHT_SPD_GGAIN        1.08
#define SN60_CWF_LPD_BGAIN           2.53
#define SN60_CWF_LPD_RGAIN           1.84
#define SN60_CWF_SPD_BGAIN           2.52
#define SN60_CWF_SPD_RGAIN           1.63
#define SN60_D65_LPD_BGAIN           1.49
#define SN60_D65_LPD_RGAIN           1.81
#define SN60_D65_SPD_BGAIN           1.59
#define SN60_D65_SPD_RGAIN           1.59

#define LCE100_ALIGHT_LPD_BGAIN    2.754266
#define LCE100_ALIGHT_LPD_RGAIN    0.898437
#define LCE100_ALIGHT_LPD_GGAIN    1
#define LCE100_ALIGHT_SPD_BGAIN    2.539249
#define LCE100_ALIGHT_SPD_RGAIN    0.898437
#define LCE100_ALIGHT_SPD_GGAIN    1
#define LCE100_CWF_LPD_BGAIN       2.539062
#define LCE100_CWF_LPD_RGAIN       1.5625
#define LCE100_CWF_SPD_BGAIN       2.472656
#define LCE100_CWF_SPD_RGAIN       1.429687
#define LCE100_D65_LPD_BGAIN       1.495781
#define LCE100_D65_LPD_RGAIN       1.81875
#define LCE100_D65_SPD_BGAIN       1.685315
#define LCE100_D65_SPD_RGAIN       1.810625

#define LCE60_ALIGHT_LPD_BGAIN     3.827586
#define LCE60_ALIGHT_LPD_RGAIN     1
#define LCE60_ALIGHT_LPD_GGAIN     1.261084
#define LCE60_ALIGHT_SPD_BGAIN     3.046083
#define LCE60_ALIGHT_SPD_RGAIN     1
#define LCE60_ALIGHT_SPD_GGAIN     1.179724
#define LCE60_CWF_LPD_BGAIN        2.546875
#define LCE60_CWF_LPD_RGAIN        1.332031
#define LCE60_CWF_SPD_BGAIN        2.589844
#define LCE60_CWF_SPD_RGAIN        1.308594
#define LCE60_D65_LPD_BGAIN        1.648438
#define LCE60_D65_LPD_RGAIN        1.441406
#define LCE60_D65_SPD_BGAIN        1.765625
#define LCE60_D65_SPD_RGAIN        1.343750

// #define OF_ALIGHT_HCG_BGAIN        3.24576
// #define OF_ALIGHT_HCG_RGAIN        1.2154
// #define OF_ALIGHT_HCG_GGAIN        1
#define OF_ALIGHT_LCG_BGAIN        3.22949
#define OF_ALIGHT_LCG_RGAIN        1.21793
#define OF_ALIGHT_LCG_GGAIN        1
// #define OF_ALIGHT_VS_BGAIN         3.2322
// #define OF_ALIGHT_VS_RGAIN         1.21483
// #define OF_ALIGHT_VS_GGAIN         1
#define OF_ALIGHT_SPD_BGAIN        2.75916
#define OF_ALIGHT_SPD_RGAIN        1.15944
#define OF_ALIGHT_SPD_GGAIN        1

// #define OF_CWF_HCG_BGAIN           2.85225
// #define OF_CWF_HCG_RGAIN           1.94073
#define OF_CWF_LCG_BGAIN           2.85018
#define OF_CWF_LCG_RGAIN           1.94843
// #define OF_CWF_VS_BGAIN            2.86158
// #define OF_CWF_VS_RGAIN            1.96501
#define OF_CWF_SPD_BGAIN           2.59799
#define OF_CWF_SPD_RGAIN           1.74538

// #define OF_D65_HCG_BGAIN           1.62327
// #define OF_D65_HCG_RGAIN           2.15482
#define OF_D65_LCG_BGAIN           1.62558
#define OF_D65_LCG_RGAIN           2.14724
// #define OF_D65_VS_BGAIN            1.64037
// #define OF_D65_VS_RGAIN            2.14096
#define OF_D65_SPD_BGAIN           1.62414
#define OF_D65_SPD_RGAIN           1.86603

#define DEFAULT_SENSOR_XCLK     24

#define DES_PORT_NUM_MAX 4U
#define RETRY_TIME_MAX  5

#define LINK_ALL                0xFFU
#define LINK_NONE               0x00

#define REG_LINK_SET_96712      0x0003
#define LINK_ALL_96712          0xAA
#define LINK_NONE_96712         0xFF

#define REG_LINK_SET_9296       0x0010
#define LINK_ALL_9296           0x23
#define LINK_NONE_9296          0x20

#define REG_TXRATE_96712_AB     0x0010
#define REG_TXRATE_96712_CD     0x0011

#define REG_TXRATE_96718_A     	0x0001
#define REG_TXRATE_96718_B     	0x0004
#define REG_LINKA_SET_96718     0x0001
#define REG_LINKB_SET_96718     0x0003
#define LINK_ALL_9296_ANY       0x31

#define REG_TXRATE_9296         0x0001

#define TXRATE_6G               0x2
#define TXRATE_3G               0x1

#define REG_ALIAS_ID_SER        0x0000
#define DEFAULT_SER_ADDR        0x80
#define HAOMO_SER_ADDR	        0x84

#define REG_DATALANE_PORTA_9296 0x44A
#define REG_DATALANE_PORTB_9296 0x48A

#define REG_STREAM_ON           0x08A0
#define FORCE_CSI_OUT_96712     BIT(7)

#define REG_DPHY_0_DATA_RATE_96712 0x415
#define REG_DPHY_1_DATA_RATE_96712 0x418
#define REG_DPHY_2_DATA_RATE_96712 0x41B
#define REG_DPHY_3_DATA_RATE_96712 0x41E
#define DATA_RATE_BASE_96712       0x20

// config_index bit[8~11] reserved for camera trig mode
#define BIT(i)		(1 << (i))
#define TEST_PATTERN_SERDES	BIT(0)
#define TEST_PATTERN	BIT(1)
#define FPS_DIV		BIT(2)
#define DPHY_PORTB		BIT(3)
#define DPHY_COPY		BIT(4)
#define DES_STREAMOFF	BIT(5)
#define AWB_DISABLE     BIT(6)
#define AE_DISABLE      BIT(7)
#define TRIG_STANDARD       BIT(8)
#define TRIG_SHUTTER_SYNC   BIT(9)
#define RES_WIDTH_1920      BIT(10)
#define RES_HEIGHT_1080     BIT(11)
#define MIRROR			BIT(12)
#define FLIP			BIT(13)
#define PWL_24BIT		BIT(14)
#define AWB_CTRL_MODE_OFFS (15)
#define DES_RX_6G			(16)
#define AWB_CTRL_MODE_MASK 0x1f
#define AWB_CTRL_RATIO_DISABLE	BIT(4)
#define AE_CTRL_MODE_MASK	0xf

#define EMBEDDED_MODE        (0xf << 17)
/* add embedded data default lines*/
#define EMBEDDED_MODE_0      BIT(17)
/* add embedded data front 2 rows, resulution same*/
#define EMBEDDED_MODE_1      BIT(18)
#define EMBEDDED_MODE_2      BIT(19)
#define EMBEDDED_MODE_3      BIT(20)

#define	PORTA_OUT BIT(21)
#define	PORTB_OUT BIT(22)

#define EXT_MASK	(0xFFFFFFC0)
#define EXT_MODE	(0x0000003FU)
#define EXT_OFFS	(6)

#define MAX9296_MFP_NUM 12u
#define MAX9296_MFP_OFFSET 3u

#define MAX96712_MFP_NUM 16u
#define MAX96712_MFP_LOOP 5u
#define MAX96712_MFP_OFFSET 0x10
#define RETRY_POC_TIMES 3
#define POC_RETRY_POLICY 1

static uint32_t max9295_ldo_enable[] = {
	0x10, 0x04, 0x04,
	0x12, 0x10, 0x10,
};

static uint8_t linkb_seri2cmap[] = {
	0x04, 0x50, 0x00, 0x01, 0x12,       // close LINKA
	0x04, 0x50, 0x00, 0x03, 0x53,       // open LINKB
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x50, 0x00, 0x01, 0x02,       // open LINKA
	0x04, 0x50, 0x00, 0x03, 0x53,       // open LINKB
};

static uint8_t alias_id_setting[CAM_MAX_NUM][25] = {
	{
		0x04, 0x80, 0x00, 0x00, 0x82,
		0x04, 0x82, 0x00, 0x42, 0xA2,
		0x04, 0x82, 0x00, 0x43, 0xA0,
		0x04, 0x82, 0x00, 0x44, 0x22,
		0x04, 0x82, 0x00, 0x45, 0x20,
	},
	{
		0x04, 0x80, 0x00, 0x00, 0x84,
		0x04, 0x84, 0x00, 0x42, 0xA4,
		0x04, 0x84, 0x00, 0x43, 0xA0,
		0x04, 0x84, 0x00, 0x44, 0x24,
		0x04, 0x84, 0x00, 0x45, 0x20,
	},
	{
		0x04, 0x80, 0x00, 0x00, 0x86,
		0x04, 0x86, 0x00, 0x42, 0xA6,
		0x04, 0x86, 0x00, 0x43, 0xA0,
		0x04, 0x86, 0x00, 0x44, 0x26,
		0x04, 0x86, 0x00, 0x45, 0x20,
	},
	{
		0x04, 0x80, 0x00, 0x00, 0x88,
		0x04, 0x88, 0x00, 0x42, 0xA8,
		0x04, 0x88, 0x00, 0x43, 0xA0,
		0x04, 0x88, 0x00, 0x44, 0x28,
		0x04, 0x88, 0x00, 0x45, 0x20,
	},
	{
		0x04, 0x80, 0x00, 0x00, 0x8a,
		0x04, 0x8a, 0x00, 0x42, 0xAA,
		0x04, 0x8a, 0x00, 0x43, 0xA0,
		0x04, 0x8a, 0x00, 0x44, 0x2a,
		0x04, 0x8a, 0x00, 0x45, 0x6C,
	},
};

static uint8_t serializer_pipez_setting[] = {
	0x04, 0x80, 0x02, 0xd3, 0x00,
	0x04, 0x80, 0x02, 0xbe, 0x90,
	0x04, 0x80, 0x02, 0xbf, 0x60,

	0x04, 0x80, 0x03, 0x30, 0x00,   // Sensor 0 set pipe Z
	0x04, 0x80, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x80, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x80, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x80, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x80, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x80, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x80, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x80, 0x03, 0x83, 0x00,
	0x04, 0x80, 0x03, 0xf0, 0x51,
	0x04, 0x80, 0x03, 0xf1, 0x09,
	0x04, 0x80, 0x05, 0x70, 0x1c,
	0x04, 0x80, 0x05, 0x70, 0x0c,
	0x04, 0x80, 0x00, 0x06, 0xb1,
	0x04, 0x80, 0x02, 0xd3, 0x90,
};

static uint8_t serializer_linkb_pipez_setting[] = {
	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xbf, 0x60,
	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 0 set pipe Z
	0x04, 0x84, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x84, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x84, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x84, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x84, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x84, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x84, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x05, 0x70, 0x1c,
	0x04, 0x84, 0x05, 0x70, 0x0c,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xd3, 0x90,
	0x04, 0x84, 0x00, 0x42, 0xA4,
	0x04, 0x84, 0x00, 0x43, 0xA0,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,
};

static uint8_t max9296_dual_setting_patch[] = {
	0x04, 0x80, 0x00, 0x5B, 0x13,
	0x04, 0x80, 0x00, 0x57, 0x11,

	0x04, 0x80, 0x00, 0x6B, 0x16,
	0x04, 0x80, 0x00, 0x73, 0x17,
	0x04, 0x80, 0x00, 0x7B, 0x36,
	0x04, 0x80, 0x00, 0x83, 0x36,
	0x04, 0x80, 0x00, 0x93, 0x36,
	0x04, 0x80, 0x00, 0x9B, 0x36,
	0x04, 0x80, 0x00, 0xA3, 0x36,
	0x04, 0x80, 0x00, 0xAB, 0x36,
	0x04, 0x80, 0x00, 0x8B, 0x36,
	0x00, 0x32,
};

uint32_t max9296_init_setting[] = {
	0x0010, 0xf1,     // reset

	0x1449, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x1549, 0x75,

	0x0313, 0x00,     // CSI output disabled
	0x0330, 0x04,     // 2x4 mode
	0x0319, 0x0c,
	0x0339, 0x80,
	0x033a, 0x42,
	0x0052, 0x01,     // PipeZ Stream ID = 1
	0x0320, 0x28,     // MIPI CSI Port A 800M
	0x0323, 0x28,     // MIPI CSI Port B 800M
	0x0325, 0x80,     // wait for a new frame
};

uint32_t max9295_init_setting[] = {
	0x02be, 0x00,
	0x0311, 0x20,  // start x/y/z/u from B,20
	0x0308, 0x62,  // x/y/z/u selected B,62
	0x0002, 0x23,  // Video transmit enable  // transmit Y,23
	0x0316, 0x6c,
	0x03f0, 0x51,
	0x0003, 0x03,
	0x0006, 0xb1,
	0x02be, 0x18,
	0x02bf, 0x60,

	0x0044, 0x20,  // map sensor addr to 0x10.
	0x0045, 0x6C,
};

uint32_t max9296_init_setting_ws[] = {
	0x0010, 0xf1,     // reset
	0x0001, 0x01,

	0x0313, 0x00,     // CSI output disabled
	0x0330, 0x04,     // 2x4 mode
	0x0319, 0x0c,
	0x0339, 0x80,
	0x033a, 0x42,
	0x0051, 0x02,     // PipeY Stream ID = 2
	0x0052, 0x01,     // PipeZ Stream ID = 1
	0x0320, 0x2C,     // MIPI CSI Port A 800M
	0x0323, 0x2C,     // MIPI CSI Port B 800M
	0x0325, 0x80,     // wait for a new frame
	0x0316, 0x2c,
	0x0002, 0xf3,
	0x044a, 0xd0,
};

uint32_t max96718_init_setting_ws[] = {
	0x0010, 0xf1,     // reset
	0x0001, 0x02,
	0x0004, 0x01,
	0x1449, 0xF5,  // Enable ErrChPwrUp, Enhance link stability
	0x1549, 0xF5,


	0x0313, 0x00,     // CSI output disabled
	0x0330, 0x04,     // 2x4 mode
	0x0319, 0x0c,
	0x0339, 0x80,
	0x033a, 0x42,
	0x0051, 0x02,     // PipeY Stream ID = 2
	0x0052, 0x01,     // PipeZ Stream ID = 1
	0x0320, 0x2C,     // MIPI CSI Port A 800M
	0x0323, 0x2C,     // MIPI CSI Port B 800M
	0x0325, 0x80,     // wait for a new frame
	0x0316, 0x2c,
	0x0002, 0xf3,
	0x044a, 0xd0,
};

uint32_t max96717_init_setting_ws[] = {
	0x0042, 0xAA,
	0X0043, 0XA0,
	0x02d3, 0x00,
	0x0002, 0x43,  // Video transmit enable pipe Z
	0x0383, 0x00,
	0x0318, 0x6c,
	0x03f1, 0x09,
	0x03f0, 0x51,
	0x0570, 0x1c,
	0x0570, 0x0c,
	0x0006, 0xb1,
	0x02bf, 0x60,
	0x02be, 0x90,
	0x02d3, 0x90,

	0x0044, 0x20,  // map sensor addr to 0x10.
	0x0045, 0x6C,
};

uint32_t max9296_phy_portb_init_setting[] = {
	0x0051, 0x01,     // PipeY Stream ID = 1
	0x0052, 0x02,     // PipeZ Stream ID = 2
};

uint32_t max9296_phy_portall_init_setting[] = {
	0x0051, 0x01,     // PipeY Stream ID = 1
	0x0052, 0x01,     // PipeZ Stream ID = 1
};

uint32_t max9296_add_max96718_init_setting[] = {
	0x0161, 0x09,
};

static uint8_t max96712_max96717_init_setting[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x10, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x11, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x18, 0xFF,     // data path reset avtive
	0x00, 0xFF,

	0x04, 0x52, 0x00, 0x18, 0x00,     // data path reset release
	0x04, 0x52, 0x04, 0x0B, 0x00,     // CSI output disabled
	0x00, 0xFF,
	0x00, 0xFF,
	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
    0x04, 0x52, 0x06, 0xC2, 0x10,
	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,

	// MAX96717 - Serializer config
	0x04, 0x80, 0x02, 0xbe, 0x90,
	0x04, 0x80, 0x02, 0xbf, 0x60,

	0x04, 0x80, 0x03, 0x30, 0x00,   // Sensor 0 set pipe Z
	0x04, 0x80, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x80, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x80, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x80, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x80, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x80, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x80, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x80, 0x03, 0x83, 0x00,
	0x04, 0x80, 0x03, 0xf0, 0x51,
	0x04, 0x80, 0x03, 0xf1, 0x09,
	0x04, 0x80, 0x05, 0x70, 0x1c,
	0x04, 0x80, 0x05, 0x70, 0x0c,
	0x04, 0x80, 0x00, 0x06, 0xb1,

	// MAX96712 - Deserializer config
	0x04, 0x52, 0x00, 0xF0, 0x62,  	// pipe0: A-Z, pipie1: B-Z.
	0x04, 0x52, 0x00, 0xF4, 0x01,    // Enable Pipe 0

	0x04, 0x52, 0x09, 0x0B, 0x07,    // Map source 0~2 for Link A
	0x04, 0x52, 0x09, 0x2D, 0x15,    // Map source to controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,    // src vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0E, 0x2C,    // dst vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,    // src frame start
	0x04, 0x52, 0x09, 0x10, 0x00,    // dst frame start
	0x04, 0x52, 0x09, 0x11, 0x01,    // src frame end
	0x04, 0x52, 0x09, 0x12, 0x01,    // dst frame end

	0x04, 0x52, 0x08, 0xA0, 0x04,    // 2x4 mode

	0x04, 0x52, 0x08, 0xA3, 0xE4,    // Map data lanes for PHY 1
	0x04, 0x52, 0x08, 0xA4, 0xE4,    // Map data lanes for PHY 0

	0x04, 0x52, 0x09, 0x0A, 0xC0,    // 4 lanes
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,

	0x04, 0x52, 0x08, 0xA2, 0x34,    // Enable MIPI PHY0~1

// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,

// Set Data rate to be 2000Mbps/lane
	0x04, 0x52, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x34,
	0x04, 0x52, 0x04, 0x1E, 0x34,

// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
};

static uint8_t max96712_reset_serial_with_3G_init[] = {
	0x04, 0x52, 0x00, 0x10, 0x11,     // Link A B 3G
	0x04, 0x52, 0x00, 0x11, 0x11,     // Link C D 3G
	0x00, 0x64,
	0x04, 0x52, 0x00, 0x18, 0xFF,     // data path reset avtive
	0x00, 0x32,
	0x04, 0x52, 0x00, 0x18, 0x00,     // data path reset release
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x06, 0xFF,     // Link A-D
	0x00, 0x64,
};

static uint8_t max96712_dms_parellel_enable[] = {
	// 0x04, 0x82, 0x00, 0x07, 0xF7, 	// Parellel enable
};
static uint8_t max96712_max96717_ovx3c_max9295_dms_init_setting_4lane[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0x64,
	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
    0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x04, 0x0B, 0x00,     // CSI output disabled
	// 0x04, 0x52, 0x04, 0x06, 0xF0,     // close all links
	0x04, 0x52, 0x00, 0x10, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x11, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x18, 0xFF,     // data path reset avtive
	0x00, 0x32,
	0x04, 0x52, 0x00, 0x18, 0x00,     // data path reset release
	0x00, 0x64,

	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0xDA,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xA4,
	0x04, 0x84, 0x00, 0x43, 0xA0,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF4,    // Link C
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x86,
	0x04, 0x86, 0x00, 0x42, 0xA6,
	0x04, 0x86, 0x00, 0x43, 0xA0,
	0x04, 0x86, 0x00, 0x44, 0x26,
	0x04, 0x86, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF8,    // Link D
	0x00, 0x80,
	0x04, 0x80, 0x00, 0x00, 0x88,
	0x04, 0x88, 0x00, 0x42, 0xA8,
	0x04, 0x88, 0x00, 0x43, 0xA0,
	0x04, 0x88, 0x00, 0x44, 0x28,
	0x04, 0x88, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xFF,   // Enable all 4 Links in GMSL2 mode
	0x00, 0x64,
	/* DVP configuration for ov2311  LINKA pipe X */
	0x04, 0x82, 0x01, 0xb0, 0x04,
	0x04, 0x82, 0x01, 0xb1, 0x05,
	0x04, 0x82, 0x01, 0xb2, 0x06,
	0x04, 0x82, 0x01, 0xb3, 0x07,
	0x04, 0x82, 0x01, 0xb4, 0x08,
	0x04, 0x82, 0x01, 0xb5, 0x09,
	0x04, 0x82, 0x01, 0xb6, 0x0a,
	0x04, 0x82, 0x01, 0xb7, 0x0b,
	0x04, 0x82, 0x00, 0x02, 0x13, 	// Turn on pipe x only
	0x04, 0x82, 0x00, 0x53, 0x02,   /* pipe x -> stream 2 0x02 */
	0x04, 0x82, 0x01, 0x00, 0x60,	/* Line-CRC enabled, HS,VS,DE encoding on */
	0x04, 0x82, 0x01, 0x01, 0x4A,	/* Color bits per pixel */

	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xbf, 0x60,

	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe Z
	0x04, 0x84, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x84, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x84, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x84, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x84, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x84, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x84, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x05, 0x70, 0x1c,
	0x04, 0x84, 0x05, 0x70, 0x0c,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xd3, 0x90,

	0x04, 0x86, 0x02, 0xd3, 0x00,
	0x04, 0x86, 0x02, 0xbe, 0x90,
	0x04, 0x86, 0x02, 0xbf, 0x60,

	0x04, 0x86, 0x03, 0x30, 0x00,   // Sensor 2 set pipe Z
	0x04, 0x86, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x86, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x86, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x86, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x86, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x86, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x86, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x86, 0x03, 0x83, 0x00,
	0x04, 0x86, 0x03, 0xf0, 0x51,
	0x04, 0x86, 0x03, 0xf1, 0x09,
	0x04, 0x86, 0x05, 0x70, 0x1c,
	0x04, 0x86, 0x05, 0x70, 0x0c,
	0x04, 0x86, 0x00, 0x06, 0xb1,
	0x04, 0x86, 0x02, 0xd3, 0x90,

	0x04, 0x88, 0x02, 0xd3, 0x00,
	0x04, 0x88, 0x02, 0xbe, 0x90,
	0x04, 0x88, 0x02, 0xbf, 0x60,

	0x04, 0x88, 0x03, 0x30, 0x00,   // Sensor 3 set pipe Z
	0x04, 0x88, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x88, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x88, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x88, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x88, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x88, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x88, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x88, 0x03, 0x83, 0x00,
	0x04, 0x88, 0x03, 0xf0, 0x51,
	0x04, 0x88, 0x03, 0xf1, 0x09,
	0x04, 0x88, 0x05, 0x70, 0x1c,
	0x04, 0x88, 0x05, 0x70, 0x0c,
	0x04, 0x88, 0x00, 0x06, 0xb1,
	0x04, 0x88, 0x02, 0xd3, 0x90,
    // pipe Z in link B to video pipe 1, pipe Z in link A to video pipe 0
	0x04, 0x52, 0x00, 0xF0, 0x62,
	// pipe Z in link D to video pipe 3, pipe Z in link C to video pipe 2
	0x04, 0x52, 0x00, 0xF1, 0xEA,

	// pipe Z in link B to video pipe 5, pipe Z in link A to video pipe 4
	0x04, 0x52, 0x00, 0xF2, 0x62,
	// pipe Z in link D to video pipe 7, pipe Z in link C to video pipe 6
	// 0x04, 0x52, 0x00, 0xF3, 0xEA,
	// 0x04, 0x52, 0x00, 0xF4, 0xFF,    // Enable Pipe 0~7
	// 0x04, 0x52, 0x08, 0xA2, 0xF4,    // Enable MIPI PHY0~3

	0x04, 0x52, 0x04, 0x0E, 0x1E,    // 0b00(DT1_H)-011110(DT0), Set DT of Pipe0(0x1E)
	0x04, 0x52, 0x04, 0x2E, 0x1E,    // 0b00(DT1_H)-011110(DT0), Set DT of Pipe4(0x1E)
	0x04, 0x52, 0x04, 0x0B, 0x40,    // 0b01000-000, Set bpp of pipe0(0x08)
	0x04, 0x52, 0x04, 0x2B, 0x40,    // 0b01000-000, Set bpp of pipe4(0x08)
	// YUV MUXED MODE for pipe 0,2
	0x04, 0x52, 0x04, 0x1A, 0x10,    // Set pipe0 YUV MUX mode
	0x04, 0x52, 0x04, 0x3A, 0x10,    // Set pipe4 YUV MUX mode

	0x04, 0x52, 0x00, 0xF4, 0x1F,    // Enable Pipe 0~4
	0x04, 0x52, 0x08, 0xA2, 0xF4,    // Enable MIPI PHY0~3
	// 0x04, 0x52, 0x00, 0x03, 0xAA,    // Enable all 4 Links in GMSL2 mode
    // close dms to J5A
	// 0x04, 0x52, 0x09, 0x0B, 0x07,    // Map source 0~2 for Link A
	// 0x04, 0x52, 0x09, 0x2D, 0x2a,    // Map source to controller 2
	// 0x04, 0x52, 0x09, 0x0D, 0x1E,    // src vc && datatype, vc = 0, RAW12
	// 0x04, 0x52, 0x09, 0x0E, 0x1E,    // dst vc && datatype, vc = 0, RAW12
	// 0x04, 0x52, 0x09, 0x0F, 0x00,    // src frame start
	// 0x04, 0x52, 0x09, 0x10, 0x00,    // dst frame start
	// 0x04, 0x52, 0x09, 0x11, 0x01,    // src frame end
	// 0x04, 0x52, 0x09, 0x12, 0x01,    // dst frame end

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x2a,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	0x04, 0x52, 0x09, 0x8B, 0x07,    // Map source 0~2 for Link C
	0x04, 0x52, 0x09, 0xAD, 0x2a,
	0x04, 0x52, 0x09, 0x8D, 0x2C,
	0x04, 0x52, 0x09, 0x8E, 0xAC,    // vc = 2
	0x04, 0x52, 0x09, 0x8F, 0x00,
	0x04, 0x52, 0x09, 0x90, 0x80,
	0x04, 0x52, 0x09, 0x91, 0x01,
	0x04, 0x52, 0x09, 0x92, 0x81,

	0x04, 0x52, 0x09, 0xCB, 0x07,    // Map source 0~2 for Link D
	0x04, 0x52, 0x09, 0xED, 0x2a,
	0x04, 0x52, 0x09, 0xCD, 0x2C,
	0x04, 0x52, 0x09, 0xCE, 0xEC,    // vc = 3
	0x04, 0x52, 0x09, 0xCF, 0x00,
	0x04, 0x52, 0x09, 0xD0, 0xC0,
	0x04, 0x52, 0x09, 0xD1, 0x01,
	0x04, 0x52, 0x09, 0xD2, 0xC1,

	0x04, 0x52, 0x08, 0xA0, 0x04,    // 2x4 mode
	0x04, 0x52, 0x08, 0xA3, 0xE4,    // Map data lanes for PHY 1
	0x04, 0x52, 0x08, 0xA4, 0xE4,    // Map data lanes for PHY 0
	0x04, 0x52, 0x09, 0x0A, 0xC0,    // 4 lanes
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,

	// open dms to J5B
	0x04, 0x52, 0x0A, 0x0B, 0x07,	 // Map source 0~2 for Link A
	0x04, 0x52, 0x0A, 0x2D, 0x15,	 // Map source to controller 1
	0x04, 0x52, 0x0A, 0x0D, 0x1E,	 // src vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x0A, 0x0E, 0x1E,	 // dst vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x0A, 0x0F, 0x00,	 // src frame start
	0x04, 0x52, 0x0A, 0x10, 0x00,	 // dst frame start
	0x04, 0x52, 0x0A, 0x11, 0x01,	 // src frame end
	0x04, 0x52, 0x0A, 0x12, 0x01,	 // dst frame end

// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,

// Set Data rate to be 2000Mbps/lane
	0x04, 0x52, 0x04, 0x15, 0x34,     // enable software-override for pipe0
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x74,    // enable software-override for pipe 4
	0x04, 0x52, 0x04, 0x1E, 0x34,

// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
	0x04, 0x82, 0x00, 0x07, 0xF7, 	// Parellel enable
};

static uint8_t max96712_max9295_ovx3c_max9295_dms_init_setting_4lane[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x04, 0x0B, 0x00,     // CSI output disabled
	0x04, 0x52, 0x00, 0x10, 0x21,     // Link A
	0x04, 0x52, 0x00, 0x11, 0x22,     // Link A
	0x04, 0x52, 0x00, 0x18, 0xFF,     // data path reset
	0x00, 0x32,
	0x04, 0x52, 0x00, 0x18, 0x00,     // data path reset release
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x15, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x52, 0x16, 0x49, 0x75,
	0x04, 0x52, 0x17, 0x49, 0x75,

    // solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
	0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	// 0x04, 0x82, 0x00, 0x44, 0x22,
	// 0x04, 0x82, 0x00, 0x45, 0xDA,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF4,    // Link C
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x86,
	0x04, 0x86, 0x00, 0x42, 0xC4,
	0x04, 0x86, 0x00, 0x43, 0x86,
	0x04, 0x86, 0x00, 0x44, 0x26,
	0x04, 0x86, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF8,    // Link D
	0x00, 0xFF,
	0x04, 0x80, 0x00, 0x00, 0x88,
	0x04, 0x88, 0x00, 0x42, 0xC4,
	0x04, 0x88, 0x00, 0x43, 0x88,
	0x04, 0x88, 0x00, 0x44, 0x28,
	0x04, 0x88, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xFF,   // Enable all 4 Links in GMSL2 mode
	0x00, 0x64,

	/* DVP configuration for ov2311  LINKA pipe X */
	0x04, 0x82, 0x01, 0xb0, 0x04,
	0x04, 0x82, 0x01, 0xb1, 0x05,
	0x04, 0x82, 0x01, 0xb2, 0x06,
	0x04, 0x82, 0x01, 0xb3, 0x07,
	0x04, 0x82, 0x01, 0xb4, 0x08,
	0x04, 0x82, 0x01, 0xb5, 0x09,
	0x04, 0x82, 0x01, 0xb6, 0x0a,
	0x04, 0x82, 0x01, 0xb7, 0x0b,
	0x04, 0x82, 0x00, 0x02, 0x13, 	// Turn on pipe x only
	0x04, 0x82, 0x00, 0x53, 0x02,   /* pipe x -> stream 2 0x02 */
	0x04, 0x82, 0x01, 0x00, 0x60,	/* Line-CRC enabled, HS,VS,DE encoding on */
	0x04, 0x82, 0x01, 0x01, 0x4A,	/* Color bits per pixel */

	0x04, 0x84, 0x02, 0xbe, 0x00,
	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe X
	0x04, 0x84, 0x03, 0x31, 0x33,
	0x04, 0x84, 0x03, 0x08, 0x61,
	0x04, 0x84, 0x03, 0x11, 0x30,
	0x04, 0x84, 0x00, 0x02, 0x33,
	0x04, 0x84, 0x03, 0x14, 0x6C,
	// 0x04, 0x84, 0x02, 0xd6, 0x09,
	0x04, 0x84, 0x02, 0xbe, 0x18,
	0x04, 0x84, 0x02, 0xbf, 0x60,

	0x04, 0x86, 0x02, 0xbe, 0x00,
	0x04, 0x86, 0x03, 0x30, 0x00,   // Sensor 2 set pipe X
	0x04, 0x86, 0x03, 0x31, 0x33,
	0x04, 0x86, 0x03, 0x08, 0x61,
	0x04, 0x86, 0x03, 0x11, 0x30,
	0x04, 0x86, 0x00, 0x02, 0x33,
	0x04, 0x86, 0x03, 0x14, 0x6C,
	// 0x04, 0x86, 0x02, 0xd6, 0x09,
	0x04, 0x86, 0x02, 0xbe, 0x18,
	0x04, 0x86, 0x02, 0xbf, 0x60,

	0x04, 0x88, 0x02, 0xbe, 0x00,
	0x04, 0x88, 0x03, 0x30, 0x00,   // Sensor 3 set pipe X
	0x04, 0x88, 0x03, 0x31, 0x33,
	0x04, 0x88, 0x03, 0x08, 0x61,
	0x04, 0x88, 0x03, 0x11, 0x30,
	0x04, 0x88, 0x00, 0x02, 0x33,
	0x04, 0x88, 0x03, 0x14, 0x6C,
	// 0x04, 0x88, 0x02, 0xd6, 0x09,
	0x04, 0x88, 0x02, 0xbe, 0x18,
	0x04, 0x88, 0x02, 0xbf, 0x60,

    // pipe Z in link B to video pipe 1, pipe Z in link A to video pipe 0
	0x04, 0x52, 0x00, 0xF0, 0x42,
	// pipe Z in link D to video pipe 3, pipe Z in link C to video pipe 2
	0x04, 0x52, 0x00, 0xF1, 0xC8,

	// pipe Z in link B to video pipe 5, pipe Z in link A to video pipe 4
	0x04, 0x52, 0x00, 0xF2, 0x62,
	0x04, 0x52, 0x04, 0x0E, 0x1E,    // 0b00(DT1_H)-011110(DT0), Set DT of Pipe0(0x1E)
	0x04, 0x52, 0x04, 0x2E, 0x1E,    // 0b00(DT1_H)-011110(DT0), Set DT of Pipe4(0x1E)
	0x04, 0x52, 0x04, 0x0B, 0x40,    // 0b01000-000, Set bpp of pipe0(0x08)
	0x04, 0x52, 0x04, 0x2B, 0x40,    // 0b01000-000, Set bpp of pipe4(0x08)
	// YUV MUXED MODE for pipe 0,2
	0x04, 0x52, 0x04, 0x1A, 0x10,    // Set pipe0 YUV MUX mode
	0x04, 0x52, 0x04, 0x3A, 0x10,    // Set pipe4 YUV MUX mode
	0x04, 0x52, 0x00, 0xF4, 0x1F,    // Enable Pipe 0~4
    0x04, 0x52, 0x08, 0xA2, 0xF4,    // Enable MIPI PHY0~3

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x2A,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	0x04, 0x52, 0x09, 0x8B, 0x07,    // Map source 0~2 for Link C
	0x04, 0x52, 0x09, 0xAD, 0x2A,
	0x04, 0x52, 0x09, 0x8D, 0x2C,
	0x04, 0x52, 0x09, 0x8E, 0xAC,    // vc = 2
	0x04, 0x52, 0x09, 0x8F, 0x00,
	0x04, 0x52, 0x09, 0x90, 0x80,
	0x04, 0x52, 0x09, 0x91, 0x01,
	0x04, 0x52, 0x09, 0x92, 0x81,

	0x04, 0x52, 0x09, 0xCB, 0x07,    // Map source 0~2 for Link D
	0x04, 0x52, 0x09, 0xED, 0x2A,
	0x04, 0x52, 0x09, 0xCD, 0x2C,
	0x04, 0x52, 0x09, 0xCE, 0xEC,    // vc = 3
	0x04, 0x52, 0x09, 0xCF, 0x00,
	0x04, 0x52, 0x09, 0xD0, 0xC0,
	0x04, 0x52, 0x09, 0xD1, 0x01,
	0x04, 0x52, 0x09, 0xD2, 0xC1,

	0x04, 0x52, 0x08, 0xA0, 0x04,    // 2x4 mode
	0x04, 0x52, 0x08, 0xA3, 0xE4,    // Map data lanes for PHY 1
	0x04, 0x52, 0x08, 0xA4, 0xE4,    // Map data lanes for PHY 0
	0x04, 0x52, 0x09, 0x0A, 0xC0,    // 4 lanes
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,
	// open dms to J5B
	0x04, 0x52, 0x0A, 0x0B, 0x07,	 // Map source 0~2 for Link A
	0x04, 0x52, 0x0A, 0x2D, 0x15,	 // Map source to controller 1
	0x04, 0x52, 0x0A, 0x0D, 0x1E,	 // src vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x0A, 0x0E, 0x1E,	 // dst vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x0A, 0x0F, 0x00,	 // src frame start
	0x04, 0x52, 0x0A, 0x10, 0x00,	 // dst frame start
	0x04, 0x52, 0x0A, 0x11, 0x01,	 // src frame end
	0x04, 0x52, 0x0A, 0x12, 0x01,	 // dst frame end

// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,

// Set Data rate to be 2000Mbps/lane
	0x04, 0x52, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x74,
	0x04, 0x52, 0x04, 0x1E, 0x34,

// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
	0x04, 0x82, 0x00, 0x07, 0xF7, 	// Parellel enable
};

static uint8_t max96712_galaxy_map_setting[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x10, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x11, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x18, 0xFF,     // data path reset avtive
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x18, 0x00,     // data path reset release
	0x04, 0x52, 0x04, 0x0B, 0x00,     // CSI output disabled
	0x00, 0xFF,
	0x00, 0xFF,
	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
    0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xA2,
	0x04, 0x82, 0x00, 0x43, 0xA0,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xA4,
	0x04, 0x84, 0x00, 0x43, 0xA0,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF4,    // Link C
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x86,
	0x04, 0x86, 0x00, 0x42, 0xA6,
	0x04, 0x86, 0x00, 0x43, 0xA0,
	0x04, 0x86, 0x00, 0x44, 0x26,
	0x04, 0x86, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF8,    // Link D
	0x00, 0x80,
	0x04, 0x80, 0x00, 0x00, 0x88,
	0x04, 0x88, 0x00, 0x42, 0xA8,
	0x04, 0x88, 0x00, 0x43, 0xA0,
	0x04, 0x88, 0x00, 0x44, 0x28,
	0x04, 0x88, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xFF,   // Enable all 4 Links in GMSL2 mode
	0x00, 0xFF,
};

static uint8_t max96712_lce_map_setting[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x10, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x11, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x18, 0xFF,     // data path reset avtive
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x18, 0x00,     // data path reset release
	0x04, 0x52, 0x04, 0x0B, 0x00,     // CSI output disabled
	0x00, 0xFF,
	0x00, 0xFF,
	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
    0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xA2,
	0x04, 0x82, 0x00, 0x43, 0xAE,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xA4,
	0x04, 0x84, 0x00, 0x43, 0xAE,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF4,    // Link C
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x86,
	0x04, 0x86, 0x00, 0x42, 0xA6,
	0x04, 0x86, 0x00, 0x43, 0xAE,
	0x04, 0x86, 0x00, 0x44, 0x26,
	0x04, 0x86, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF8,    // Link D
	0x00, 0x80,
	0x04, 0x80, 0x00, 0x00, 0x88,
	0x04, 0x88, 0x00, 0x42, 0xA8,
	0x04, 0x88, 0x00, 0x43, 0xAE,
	0x04, 0x88, 0x00, 0x44, 0x28,
	0x04, 0x88, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xFF,   // Enable all 4 Links in GMSL2 mode
	0x00, 0xFF,
};

static uint8_t max96712_ofilm_map_setting[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x10, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x11, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x18, 0xFF,     // data path reset avtive
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x18, 0x00,     // data path reset release
	0x04, 0x52, 0x04, 0x0B, 0x00,     // CSI output disabled
	0x00, 0xFF,
	0x00, 0xFF,
	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
    0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x84, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xA2,
	0x04, 0x82, 0x00, 0x43, 0xAE,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x84, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xA4,
	0x04, 0x84, 0x00, 0x43, 0xAE,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF4,    // Link C
	0x00, 0x32,
	0x04, 0x84, 0x00, 0x00, 0x86,
	0x04, 0x86, 0x00, 0x42, 0xA6,
	0x04, 0x86, 0x00, 0x43, 0xAE,
	0x04, 0x86, 0x00, 0x44, 0x26,
	0x04, 0x86, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF8,    // Link D
	0x00, 0x80,
	0x04, 0x84, 0x00, 0x00, 0x88,
	0x04, 0x88, 0x00, 0x42, 0xA8,
	0x04, 0x88, 0x00, 0x43, 0xAE,
	0x04, 0x88, 0x00, 0x44, 0x28,
	0x04, 0x88, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xFF,   // Enable all 4 Links in GMSL2 mode
	0x00, 0xFF,
};

static uint8_t max96712_max96717_quad_init_setting_4lane[] = {
	0x04, 0x82, 0x02, 0xd3, 0x00,
	0x04, 0x82, 0x02, 0xbe, 0x90,
	0x04, 0x82, 0x02, 0xbf, 0x60,

	0x04, 0x82, 0x03, 0x30, 0x00,   // Sensor 0 set pipe Z
	0x04, 0x82, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x82, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x82, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x82, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x82, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x82, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x82, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x82, 0x03, 0x83, 0x00,
	0x04, 0x82, 0x03, 0xf0, 0x51,
	0x04, 0x82, 0x03, 0xf1, 0x09,
	0x04, 0x82, 0x05, 0x70, 0x1c,
	0x04, 0x82, 0x05, 0x70, 0x0c,
	0x04, 0x82, 0x00, 0x06, 0xb1,
	0x04, 0x82, 0x02, 0xd3, 0x90,

	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xbf, 0x60,

	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe Z
	0x04, 0x84, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x84, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x84, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x84, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x84, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x84, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x84, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x05, 0x70, 0x1c,
	0x04, 0x84, 0x05, 0x70, 0x0c,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xd3, 0x90,

	0x04, 0x86, 0x02, 0xd3, 0x00,
	0x04, 0x86, 0x02, 0xbe, 0x90,
	0x04, 0x86, 0x02, 0xbf, 0x60,

	0x04, 0x86, 0x03, 0x30, 0x00,   // Sensor 2 set pipe Z
	0x04, 0x86, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x86, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x86, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x86, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x86, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x86, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x86, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x86, 0x03, 0x83, 0x00,
	0x04, 0x86, 0x03, 0xf0, 0x51,
	0x04, 0x86, 0x03, 0xf1, 0x09,
	0x04, 0x86, 0x05, 0x70, 0x1c,
	0x04, 0x86, 0x05, 0x70, 0x0c,
	0x04, 0x86, 0x00, 0x06, 0xb1,
	0x04, 0x86, 0x02, 0xd3, 0x90,

	0x04, 0x88, 0x02, 0xd3, 0x00,
	0x04, 0x88, 0x02, 0xbe, 0x90,
	0x04, 0x88, 0x02, 0xbf, 0x60,

	0x04, 0x88, 0x03, 0x30, 0x00,   // Sensor 3 set pipe Z
	0x04, 0x88, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x88, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x88, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x88, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x88, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x88, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x88, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x88, 0x03, 0x83, 0x00,
	0x04, 0x88, 0x03, 0xf0, 0x51,
	0x04, 0x88, 0x03, 0xf1, 0x09,
	0x04, 0x88, 0x05, 0x70, 0x1c,
	0x04, 0x88, 0x05, 0x70, 0x0c,
	0x04, 0x88, 0x00, 0x06, 0xb1,
	0x04, 0x88, 0x02, 0xd3, 0x90,

// pipe X in link B to video pipe 1, pipe X in link A to video pipe 0
	0x04, 0x52, 0x00, 0xF0, 0x62,
// pipe X in link D to video pipe 3, pipe X in link C to video pipe 2
	0x04, 0x52, 0x00, 0xF1, 0xEA,

	0x04, 0x52, 0x00, 0xF4, 0x0F,    // Enable Pipe 0~3

	0x04, 0x52, 0x09, 0x0B, 0x07,    // Map source 0~2 for Link A
	0x04, 0x52, 0x09, 0x2D, 0x15,    // Map source to controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,    // src vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0E, 0x2C,    // dst vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,    // src frame start
	0x04, 0x52, 0x09, 0x10, 0x00,    // dst frame start
	0x04, 0x52, 0x09, 0x11, 0x01,    // src frame end
	0x04, 0x52, 0x09, 0x12, 0x01,    // dst frame end

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x15,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	0x04, 0x52, 0x09, 0x8B, 0x07,    // Map source 0~2 for Link C
	0x04, 0x52, 0x09, 0xAD, 0x15,
	0x04, 0x52, 0x09, 0x8D, 0x2C,
	0x04, 0x52, 0x09, 0x8E, 0xAC,    // vc = 2
	0x04, 0x52, 0x09, 0x8F, 0x00,
	0x04, 0x52, 0x09, 0x90, 0x80,
	0x04, 0x52, 0x09, 0x91, 0x01,
	0x04, 0x52, 0x09, 0x92, 0x81,

	0x04, 0x52, 0x09, 0xCB, 0x07,    // Map source 0~2 for Link D
	0x04, 0x52, 0x09, 0xED, 0x15,
	0x04, 0x52, 0x09, 0xCD, 0x2C,
	0x04, 0x52, 0x09, 0xCE, 0xEC,    // vc = 3
	0x04, 0x52, 0x09, 0xCF, 0x00,
	0x04, 0x52, 0x09, 0xD0, 0xC0,
	0x04, 0x52, 0x09, 0xD1, 0x01,
	0x04, 0x52, 0x09, 0xD2, 0xC1,

	0x04, 0x52, 0x08, 0xA0, 0x04,    // 2x4 mode

	0x04, 0x52, 0x08, 0xA3, 0xE4,    // Map data lanes for PHY 1
	0x04, 0x52, 0x08, 0xA4, 0xE4,    // Map data lanes for PHY 0

	0x04, 0x52, 0x09, 0x0A, 0xC0,    // 4 lanes
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,

	0x04, 0x52, 0x08, 0xA2, 0x34,    // Enable MIPI PHY0~1

// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,

// Set Data rate to be 2000Mbps/lane
	0x04, 0x52, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x34,
	0x04, 0x52, 0x04, 0x1E, 0x34,

// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
};

static uint8_t max96712_max96717_dual_init_setting_4lane[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x10, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x11, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x18, 0xFF,     // data path reset avtive
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x18, 0x00,     // data path reset release
	0x04, 0x52, 0x04, 0x0B, 0x00,     // CSI output disabled
	0x00, 0xFF,
	0x00, 0xFF,
	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
	0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF3,   // Enable A+B Links in GMSL2 mode
	0x00, 0xFF,
	0x04, 0x82, 0x02, 0xd3, 0x00,
	0x04, 0x82, 0x02, 0xbe, 0x90,
	0x04, 0x82, 0x02, 0xbf, 0x60,

	0x04, 0x82, 0x03, 0x30, 0x00,   // Sensor 0 set pipe Z
	0x04, 0x82, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x82, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x82, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x82, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x82, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x82, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x82, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x82, 0x03, 0x83, 0x00,
	0x04, 0x82, 0x03, 0xf0, 0x51,
	0x04, 0x82, 0x03, 0xf1, 0x09,
	0x04, 0x82, 0x05, 0x70, 0x1c,
	0x04, 0x82, 0x05, 0x70, 0x0c,
	0x04, 0x82, 0x00, 0x06, 0xb1,
	0x04, 0x82, 0x02, 0xd3, 0x90,

	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xbf, 0x60,

	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe Z
	0x04, 0x84, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x84, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x84, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x84, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x84, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x84, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x84, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x05, 0x70, 0x1c,
	0x04, 0x84, 0x05, 0x70, 0x0c,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xd3, 0x90,

// pipe X in link B to video pipe 1, pipe X in link A to video pipe 0
	0x04, 0x52, 0x00, 0xF0, 0x62,

	0x04, 0x52, 0x00, 0xF4, 0x03,    // Enable Pipe 0~1

	0x04, 0x52, 0x09, 0x0B, 0x07,    // Map source 0~2 for Link A
	0x04, 0x52, 0x09, 0x2D, 0x15,    // Map source to controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,    // src vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0E, 0x2C,    // dst vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,    // src frame start
	0x04, 0x52, 0x09, 0x10, 0x00,    // dst frame start
	0x04, 0x52, 0x09, 0x11, 0x01,    // src frame end
	0x04, 0x52, 0x09, 0x12, 0x01,    // dst frame end

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x15,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	0x04, 0x52, 0x08, 0xA0, 0x04,    // 2x4 mode

	0x04, 0x52, 0x08, 0xA3, 0xE4,    // Map data lanes for PHY 1
	0x04, 0x52, 0x08, 0xA4, 0xE4,    // Map data lanes for PHY 0

	0x04, 0x52, 0x09, 0x0A, 0xC0,    // 4 lanes
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,

	0x04, 0x52, 0x08, 0xA2, 0x34,    // Enable MIPI PHY0~1

// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,

// Set Data rate to be 2000Mbps/lane
	0x04, 0x52, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x34,
	0x04, 0x52, 0x04, 0x1E, 0x34,

// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
};

static uint8_t max96712_max96717_trip_init_setting_4lane[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x10, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x11, 0x11,     // Link A
	0x04, 0x52, 0x00, 0x18, 0xFF,     // data path reset avtive
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x18, 0x00,     // data path reset release
	0x04, 0x52, 0x04, 0x0B, 0x00,     // CSI output disabled
	0x00, 0xFF,
	0x00, 0xFF,
	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
    0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF4,    // Link C
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x86,
	0x04, 0x86, 0x00, 0x42, 0xC4,
	0x04, 0x86, 0x00, 0x43, 0x86,
	0x04, 0x86, 0x00, 0x44, 0x26,
	0x04, 0x86, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF7,   // Enable A+B+C Links in GMSL2 mode
	0x00, 0xFF,
	0x04, 0x82, 0x02, 0xd3, 0x00,
	0x04, 0x82, 0x02, 0xbe, 0x90,
	0x04, 0x82, 0x02, 0xbf, 0x60,

	0x04, 0x82, 0x03, 0x30, 0x00,   // Sensor 0 set pipe Z
	0x04, 0x82, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x82, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x82, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x82, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x82, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x82, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x82, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x82, 0x03, 0x83, 0x00,
	0x04, 0x82, 0x03, 0xf0, 0x51,
	0x04, 0x82, 0x03, 0xf1, 0x09,
	0x04, 0x82, 0x05, 0x70, 0x1c,
	0x04, 0x82, 0x05, 0x70, 0x0c,
	0x04, 0x82, 0x00, 0x06, 0xb1,
	0x04, 0x82, 0x02, 0xd3, 0x90,

	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xbf, 0x60,

	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe Z
	0x04, 0x84, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x84, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x84, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x84, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x84, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x84, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x84, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x05, 0x70, 0x1c,
	0x04, 0x84, 0x05, 0x70, 0x0c,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xd3, 0x90,

	0x04, 0x86, 0x02, 0xd3, 0x00,
	0x04, 0x86, 0x02, 0xbe, 0x90,
	0x04, 0x86, 0x02, 0xbf, 0x60,

	0x04, 0x86, 0x03, 0x30, 0x00,   // Sensor 2 set pipe Z
	0x04, 0x86, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x86, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x86, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x86, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x86, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x86, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x86, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x86, 0x03, 0x83, 0x00,
	0x04, 0x86, 0x03, 0xf0, 0x51,
	0x04, 0x86, 0x03, 0xf1, 0x09,
	0x04, 0x86, 0x05, 0x70, 0x1c,
	0x04, 0x86, 0x05, 0x70, 0x0c,
	0x04, 0x86, 0x00, 0x06, 0xb1,
	0x04, 0x86, 0x02, 0xd3, 0x90,

// pipe X in link B to video pipe 1, pipe X in link A to video pipe 0
	0x04, 0x52, 0x00, 0xF0, 0x62,
// pipe X in link D to video pipe 3, pipe X in link C to video pipe 2
	0x04, 0x52, 0x00, 0xF1, 0xEA,

	0x04, 0x52, 0x00, 0xF4, 0x07,    // Enable Pipe 0~2

	0x04, 0x52, 0x09, 0x0B, 0x07,    // Map source 0~2 for Link A
	0x04, 0x52, 0x09, 0x2D, 0x15,    // Map source to controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,    // src vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0E, 0x2C,    // dst vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,    // src frame start
	0x04, 0x52, 0x09, 0x10, 0x00,    // dst frame start
	0x04, 0x52, 0x09, 0x11, 0x01,    // src frame end
	0x04, 0x52, 0x09, 0x12, 0x01,    // dst frame end

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x15,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	0x04, 0x52, 0x09, 0x8B, 0x07,    // Map source 0~2 for Link C
	0x04, 0x52, 0x09, 0xAD, 0x15,
	0x04, 0x52, 0x09, 0x8D, 0x2C,
	0x04, 0x52, 0x09, 0x8E, 0xAC,    // vc = 2
	0x04, 0x52, 0x09, 0x8F, 0x00,
	0x04, 0x52, 0x09, 0x90, 0x80,
	0x04, 0x52, 0x09, 0x91, 0x01,
	0x04, 0x52, 0x09, 0x92, 0x81,

	0x04, 0x52, 0x08, 0xA0, 0x04,    // 2x4 mode

	0x04, 0x52, 0x08, 0xA3, 0xE4,    // Map data lanes for PHY 1
	0x04, 0x52, 0x08, 0xA4, 0xE4,    // Map data lanes for PHY 0

	0x04, 0x52, 0x09, 0x0A, 0xC0,    // 4 lanes
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,

	0x04, 0x52, 0x08, 0xA2, 0x34,    // Enable MIPI PHY0~1

// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,

// Set Data rate to be 2000Mbps/lane
	0x04, 0x52, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x34,
	0x04, 0x52, 0x04, 0x1E, 0x34,

// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
};

static uint8_t max96712_max96717_trip_sunny_init_setting_4lane[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x10, 0x11,     // Link A B
	0x04, 0x52, 0x00, 0x11, 0x11,     // Link C D
	0x04, 0x52, 0x00, 0x18, 0xFF,     // data path reset avtive
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x18, 0x00,     // data path reset release
	0x04, 0x52, 0x04, 0x0B, 0x00,     // CSI output disabled
	0x00, 0xFF,
	0x00, 0xFF,
	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
    0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xA4,
	0x04, 0x84, 0x00, 0x43, 0xA0,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF4,    // Link C
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x86,
	0x04, 0x86, 0x00, 0x42, 0xA6,
	0x04, 0x86, 0x00, 0x43, 0xA0,
	0x04, 0x86, 0x00, 0x44, 0x26,
	0x04, 0x86, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF8,    // Link D
	0x00, 0x80,
	0x04, 0x80, 0x00, 0x00, 0x88,
	0x04, 0x88, 0x00, 0x42, 0xA8,
	0x04, 0x88, 0x00, 0x43, 0xA0,
	0x04, 0x88, 0x00, 0x44, 0x28,
	0x04, 0x88, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xFE,   // Enable all 4 Links in GMSL2 mode
	0x00, 0xFF,

	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xbf, 0x60,

	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe Z
	0x04, 0x84, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x84, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x84, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x84, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x84, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x84, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x84, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x05, 0x70, 0x1c,
	0x04, 0x84, 0x05, 0x70, 0x0c,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xd3, 0x90,

	0x04, 0x86, 0x02, 0xd3, 0x00,
	0x04, 0x86, 0x02, 0xbe, 0x90,
	0x04, 0x86, 0x02, 0xbf, 0x60,

	0x04, 0x86, 0x03, 0x30, 0x00,   // Sensor 2 set pipe Z
	0x04, 0x86, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x86, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x86, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x86, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x86, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x86, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x86, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x86, 0x03, 0x83, 0x00,
	0x04, 0x86, 0x03, 0xf0, 0x51,
	0x04, 0x86, 0x03, 0xf1, 0x09,
	0x04, 0x86, 0x05, 0x70, 0x1c,
	0x04, 0x86, 0x05, 0x70, 0x0c,
	0x04, 0x86, 0x00, 0x06, 0xb1,
	0x04, 0x86, 0x02, 0xd3, 0x90,

	0x04, 0x88, 0x02, 0xd3, 0x00,
	0x04, 0x88, 0x02, 0xbe, 0x90,
	0x04, 0x88, 0x02, 0xbf, 0x60,

	0x04, 0x88, 0x03, 0x30, 0x00,   // Sensor 3 set pipe Z
	0x04, 0x88, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x88, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x88, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x88, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x88, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x88, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x88, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x88, 0x03, 0x83, 0x00,
	0x04, 0x88, 0x03, 0xf0, 0x51,
	0x04, 0x88, 0x03, 0xf1, 0x09,
	0x04, 0x88, 0x05, 0x70, 0x1c,
	0x04, 0x88, 0x05, 0x70, 0x0c,
	0x04, 0x88, 0x00, 0x06, 0xb1,
	0x04, 0x88, 0x02, 0xd3, 0x90,

// pipe X in link B to video pipe 1, pipe X in link A to video pipe 0
	0x04, 0x52, 0x00, 0xF0, 0x62,
// pipe X in link D to video pipe 3, pipe X in link C to video pipe 2
	0x04, 0x52, 0x00, 0xF1, 0xEA,

	0x04, 0x52, 0x00, 0xF4, 0x0E,    // Enable Pipe 1~3

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x2A,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	0x04, 0x52, 0x09, 0x8B, 0x07,    // Map source 0~2 for Link C
	0x04, 0x52, 0x09, 0xAD, 0x2A,
	0x04, 0x52, 0x09, 0x8D, 0x2C,
	0x04, 0x52, 0x09, 0x8E, 0xAC,    // vc = 2
	0x04, 0x52, 0x09, 0x8F, 0x00,
	0x04, 0x52, 0x09, 0x90, 0x80,
	0x04, 0x52, 0x09, 0x91, 0x01,
	0x04, 0x52, 0x09, 0x92, 0x81,

	0x04, 0x52, 0x09, 0xCB, 0x07,    // Map source 0~2 for Link D
	0x04, 0x52, 0x09, 0xED, 0x2A,
	0x04, 0x52, 0x09, 0xCD, 0x2C,
	0x04, 0x52, 0x09, 0xCE, 0xEC,    // vc = 3
	0x04, 0x52, 0x09, 0xCF, 0x00,
	0x04, 0x52, 0x09, 0xD0, 0xC0,
	0x04, 0x52, 0x09, 0xD1, 0x01,
	0x04, 0x52, 0x09, 0xD2, 0xC1,

	0x04, 0x52, 0x08, 0xA0, 0x04,    // 2x4 mode

	0x04, 0x52, 0x08, 0xA3, 0xE4,    // Map data lanes for PHY 1
	0x04, 0x52, 0x08, 0xA4, 0xE4,    // Map data lanes for PHY 0

	0x04, 0x52, 0x09, 0x0A, 0xC0,    // 4 lanes
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,

	0x04, 0x52, 0x08, 0xA2, 0xC4,    // Enable MIPI PHY0~1

// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,

// Set Data rate to be 2000Mbps/lane
	0x04, 0x52, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x34,
	0x04, 0x52, 0x04, 0x1E, 0x34,

// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
};

static uint8_t max96712_phy_portb_init_setting[] = {
	0x04, 0x52, 0x08, 0xA2, 0xC4,    // Enable MIPI PHY2~3
	0x04, 0x52, 0x09, 0x2D, 0x2A,    // Map pipe0 to controller 2
	0x04, 0x52, 0x09, 0x6D, 0x2A,    // Map pipe1 to controller 2
	0x04, 0x52, 0x09, 0xAD, 0x2A,    // Map pipe2 to controller 2
	0x04, 0x52, 0x09, 0xED, 0x2A,    // Map pipe3 to controller 2
};

static uint8_t max96712_phy_cpA2B_init_setting[] = {
	0x04, 0x52, 0x08, 0xA2, 0xF4,    // Enable MIPI PHY0~3
	0x04, 0x52, 0x08, 0xA9, 0xE8,    // Enable phy1 cp to phy3
};

static uint8_t max96712_phy_cpB2A_init_setting[] = {
	0x04, 0x52, 0x08, 0xA2, 0xF4,    // Enable MIPI PHY0~3
	0x04, 0x52, 0x08, 0xA9, 0xB8,    // Enable phy3 cp to phy1
};

static uint8_t max96717_mfp5_3_errb_mapping_max96718_mfp0_6_setting[] = {
	//  sensor1 errb -> 96717 mfp5 -> 96718 mfp0
	0x04, 0x82, 0x02, 0xcd, 0xeb,     // sensor0 errb
	0x04, 0x82, 0x02, 0xce, 0xa3,
	0x04, 0x90, 0x02, 0xB0, 0xf4,
	0x04, 0x90, 0x02, 0xB1, 0x63,
	0x04, 0x90, 0x02, 0xB2, 0x03,

	//  sensor2 errb -> 96717f mfp3 -> 96718 mfp6
	0x04, 0x84, 0x02, 0xc7, 0x83,
	0x04, 0x84, 0x02, 0xc8, 0xa4,
	0x04, 0x90, 0x02, 0xc2, 0x80,  // output driver enable
	0x04, 0x90, 0x52, 0xc2, 0x04,
	0x04, 0x90, 0x52, 0xc4, 0x44,

	//  modify max96718 mfp6 for gpio mode
	0x04, 0x90, 0x00, 0x03, 0x43,
};

static uint8_t max96717_mfp3_errb_mapping_max96718_mfp6_setting[] = {
	//  sensor2 errb -> 96717f mfp3 -> 96718 mfp6
	0x04, 0x84, 0x02, 0xc7, 0x83,
	0x04, 0x84, 0x02, 0xc8, 0xa4,
	0x04, 0x50, 0x02, 0xc2, 0x80,  // output driver enable
	0x04, 0x50, 0x52, 0xc2, 0x04,
	0x04, 0x50, 0x52, 0xc4, 0x44,

	//  modify max96718 mfp6 for gpio mode
	0x04, 0x50, 0x00, 0x03, 0x43,
};

static uint8_t max96717_mfp6_5_errb_mapping_max96718_mfp0_6_setting[] = {
	//  sensor1 errb -> 96717 mfp6 -> 96718 mfp0
	0x04, 0x82, 0x02, 0xd0, 0xeb,     // sensor0 errb
	0x04, 0x82, 0x02, 0xd1, 0xa3,
	0x04, 0x90, 0x02, 0xB0, 0xf4,
	0x04, 0x90, 0x02, 0xB1, 0x63,
	0x04, 0x90, 0x02, 0xB2, 0x03,

	//  sensor2 errb -> 96717f mfp5 -> 96718 mfp6
	0x04, 0x84, 0x02, 0xcd, 0x8b,
	0x04, 0x84, 0x02, 0xce, 0xa4,
	0x04, 0x90, 0x02, 0xc2, 0x80,  // output driver enable
	0x04, 0x90, 0x52, 0xc2, 0x04,
	0x04, 0x90, 0x52, 0xc4, 0x44,

	//  modify max96718 mfp6 for gpio mode
	0x04, 0x90, 0x00, 0x03, 0x43,
};

static uint8_t max96717_mfp3_errb_mapping_max96712_setting[] = {
	// sensor1 errb -> 96717 mfp3 -> 96712 mfp0
	0x04, 0x82, 0x02, 0xc7, 0x83,
	0x04, 0x82, 0x02, 0xc8, 0x82,
	0x04, 0x52, 0x03, 0x00, 0x84,
	0x04, 0x52, 0x03, 0x01, 0x60,
	0x04, 0x52, 0x03, 0x02, 0x22,

	// sensor2 errb -> 96717 mfp3 -> 96712 mfp5
	0x04, 0x84, 0x02, 0xc7, 0x83,
	0x04, 0x84, 0x02, 0xc8, 0x83,
	0x04, 0x52, 0x03, 0x10, 0x80,
	0x04, 0x52, 0x03, 0x47, 0x00,
	0x04, 0x52, 0x03, 0x48, 0x23,

	// sensor3 errb -> 96717 mfp3 -> 96712 mfp7
	0x04, 0x86, 0x02, 0xc7, 0x83,
	0x04, 0x86, 0x02, 0xc8, 0x84,
	0x04, 0x52, 0x03, 0x16, 0x80,
	0x04, 0x52, 0x03, 0x84, 0x00,
	0x04, 0x52, 0x03, 0x85, 0x24,

	// sensor4 errb -> 96717 mfp3 -> 96712 mfp9
	0x04, 0x88, 0x02, 0xc7, 0x83,
	0x04, 0x88, 0x02, 0xc8, 0x85,
	0x04, 0x52, 0x03, 0x1c, 0x80,
	0x04, 0x52, 0x03, 0xc1, 0x00,
	0x04, 0x52, 0x03, 0xc2, 0x25,
};

static uint8_t trip_max96717_mfp3_errb_mapping_max96712_setting[] = {
	// sensor2 errb -> 96717 mfp3 -> 96712 mfp5
	0x04, 0x84, 0x02, 0xc7, 0x83,
	0x04, 0x84, 0x02, 0xc8, 0x83,
	0x04, 0x52, 0x03, 0x10, 0x80,
	0x04, 0x52, 0x03, 0x47, 0x00,
	0x04, 0x52, 0x03, 0x48, 0x23,

	// sensor3 errb -> 96717 mfp3 -> 96712 mfp7
	0x04, 0x86, 0x02, 0xc7, 0x83,
	0x04, 0x86, 0x02, 0xc8, 0x84,
	0x04, 0x52, 0x03, 0x16, 0x80,
	0x04, 0x52, 0x03, 0x84, 0x00,
	0x04, 0x52, 0x03, 0x85, 0x24,

	// sensor4 errb -> 96717 mfp3 -> 96712 mfp9
	0x04, 0x88, 0x02, 0xc7, 0x83,
	0x04, 0x88, 0x02, 0xc8, 0x85,
	0x04, 0x52, 0x03, 0x1c, 0x80,
	0x04, 0x52, 0x03, 0xc1, 0x00,
	0x04, 0x52, 0x03, 0xc2, 0x25,
};

static uint8_t max96717_mfp6_errb_mapping_max96712_setting[] = {
	// sensor1 errb -> 96717 mfp6 -> 96712 mfp0
	0x04, 0x82, 0x02, 0xd0, 0x83,
	0x04, 0x82, 0x02, 0xd1, 0x82,
	0x04, 0x52, 0x03, 0x00, 0x84,
	0x04, 0x52, 0x03, 0x01, 0x60,
	0x04, 0x52, 0x03, 0x02, 0x22,

	// sensor2 errb -> 96717 mfp6 -> 96712 mfp5
	0x04, 0x84, 0x02, 0xd0, 0x83,
	0x04, 0x84, 0x02, 0xd1, 0x83,
	0x04, 0x52, 0x03, 0x10, 0x80,
	0x04, 0x52, 0x03, 0x47, 0x00,
	0x04, 0x52, 0x03, 0x48, 0x23,

	// sensor3 errb -> 96717 mfp6 -> 96712 mfp7
	0x04, 0x86, 0x02, 0xd0, 0x83,
	0x04, 0x86, 0x02, 0xd1, 0x84,
	0x04, 0x52, 0x03, 0x16, 0x80,
	0x04, 0x52, 0x03, 0x84, 0x00,
	0x04, 0x52, 0x03, 0x85, 0x24,

	// sensor4 errb -> 96717 mfp6 -> 96712 mfp9
	0x04, 0x88, 0x02, 0xd0, 0x83,
	0x04, 0x88, 0x02, 0xd1, 0x85,
	0x04, 0x52, 0x03, 0x1c, 0x80,
	0x04, 0x52, 0x03, 0xc1, 0x00,
	0x04, 0x52, 0x03, 0xc2, 0x25,
};
uint32_t max9295_max96717_trigger_mfp0_setting[] = {
	0x02BE, 0xf4,  // 1M,High prio,Jitter,ouput 1,GMSL2 rx,ouput en
	0x02BF, 0x67,  // pullup,push-pull,id = 7
	0x02C0, 0x07,  // id = 7
};

uint32_t lce_max9295_max96717_trigger_mfp0_setting[] = {
	0x02BE, 0xf4,  // 1M,High prio,Jitter,ouput 1,GMSL2 rx,ouput en
	0x02BF, 0x69,  // pullup,push-pull,id = 9
	0x02C0, 0x09,  // id = 9
};

uint32_t max9295_trigger_setting[] = {
	// 0x02D4, 0x67,  // pullup,push-pull,id = 7
	// 0x02D5, 0x07,  // id = 7
	// 0x02D3, 0xf4,  // 1M,High prio,Jitter,ouput 1,GMSL2 rx,ouput en
	0x02D7, 0x67,  // pullup,push-pull,id = 7
	0x02D8, 0x07,  // id = 7
	0x02D6, 0xf4,  // 1M,High prio,Jitter,ouput 1,GMSL2 rx,ouput en
};

uint32_t max9295_trigger_setting_mfp7[] = {
    0x02D4, 0x67,  // pullup,push-pull,id = 7
    0x02D5, 0x07,  // id = 7
    0x02D3, 0xf4,  // 1M,High prio,Jitter,ouput 1,GMSL2 rx,ouput en
};

uint32_t max9295_max96717_trigger_mfp8[] = {
	0x02D7, 0x67,  // pullup,push-pull,id = 8
	0x02D8, 0x07,  // id = 8
	0x02D6, 0xf4,  // 1M,High prio,Jitter,ouput 1,GMSL2 rx,ouput en
};

static uint16_t max9296_trigger_mfp[] = {
	0x02B1, 0xa7,  // pulldown,push-pull,id = 7
	0x02B2, 0x07,  // id = 7
	0x02B0, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
};

static uint16_t max96718_trigger_mfp[] = {
	0x02B0, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
	0x02B1, 0xa7,  // pulldown,push-pull,id = 7
	0x02B2, 0x07,  // id = 7
	0x52B0, 0xeb,  // prio,Jitter,output 0,GMSL2 tx for linkB
	0x52B1, 0xa7,  // id = 7
	0x52B2, 0x07,  // id = 7
};

/* for lce id 2 triggle */
static uint16_t lce_max96718_max96717_trigger_mfp[] = {
	0x52c5, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx mfp7 linkb x8b
	0x52c6, 0xa7,  // pulldown,push-pull,id = 7
	0x52c7, 0x07,  // id = 7
	0x02ce, 0xeb,  // prio,Jitter,output 0,GMSL2 tx for mfp10 linka x3c
	0x02cf, 0xa9,  // id = 9
	0x02d0, 0x09,  // id = 9
};

static uint16_t max9296_trigger_mfp8[] = {
	0x02C9, 0xa7,  // pulldown,push-pull,id = 7
	0x02Ca, 0x07,  // id = 7
	0x02C8, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
};

static uint16_t max9296_trigger_mfp7[] = {
	0x02C6, 0xa7,  // pulldown,push-pull,id = 7
	0x02C7, 0x07,  // id = 7
	0x02C5, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
};

static uint16_t max9296_trigger_mfp5[] = {
	0x0003, 0x40,  // pulldown,push-pull,id = 7
	0x02C0, 0xa7,  // pulldown,push-pull,id = 7
	0x02C1, 0x07,  // id = 7
	0x02bf, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
};

static uint16_t max96712_trigger_setting_mfp[] = {
//MFP0
	0x0301, 0xa7,  // pulldown,push-pull,id = 7
	0x0302, 0x07,  // id = 7
	0x0300, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
	0x0337, 0xe7,  // linkB,High prio,Jitter,GMSL2 tx,id = 7
	0x0338, 0x07,  // linkB,disable GMSL2 rx, id = 7
	0x036D, 0xe7,  // linkC,High prio,Jitter,GMSL2 tx,id = 7
	0x036E, 0x07,  // linkC,disable GMSL2 rx, id = 7
	0x03A4, 0xe7,  // linkD,High prio,Jitter,GMSL2 tx,id = 7
	0x03A5, 0x07,  // linkD,disable GMSL2 rx, id = 7
//MFP1
	0x0304, 0xa7,  // pulldown,push-pull,id = 7
	0x0305, 0x07,  // id = 7
	0x0303, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
	0x033A, 0xe7,  // linkB,High prio,Jitter,GMSL2 tx,id = 7
	0x033B, 0x07,  // linkB,disable GMSL2 rx, id = 7
	0x0371, 0xe7,  // linkC,High prio,Jitter,GMSL2 tx,id = 7
	0x0372, 0x07,  // linkC,disable GMSL2 rx, id = 7
	0x03A7, 0xe7,  // linkD,High prio,Jitter,GMSL2 tx,id = 7
	0x03A8, 0x07,  // linkD,disable GMSL2 rx, id = 7
//MFP2
	0x0307, 0xa7,  // pulldown,push-pull,id = 7
	0x0308, 0x07,  // id = 7
	0x0306, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
	0x033D, 0xe7,  // linkB,High prio,Jitter,GMSL2 tx,id = 7
	0x033E, 0x07,  // linkB,disable GMSL2 rx, id = 7
	0x0374, 0xe7,  // linkC,High prio,Jitter,GMSL2 tx,id = 7
	0x0375, 0x07,  // linkC,disable GMSL2 rx, id = 7
	0x03AA, 0xe7,  // linkD,High prio,Jitter,GMSL2 tx,id = 7
	0x03AB, 0x07,  // linkD,disable GMSL2 rx, id = 7
//MFP3
	0x030A, 0xa7,  // pulldown,push-pull,id = 7
	0x030B, 0x07,  // id = 7
	0x0309, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
	0x0341, 0xe7,  // linkB,High prio,Jitter,GMSL2 tx,id = 7
	0x0342, 0x07,  // linkB,disable GMSL2 rx, id = 7
	0x0377, 0xe7,  // linkC,High prio,Jitter,GMSL2 tx,id = 7
	0x0378, 0x07,  // linkC,disable GMSL2 rx, id = 7
	0x03AD, 0xe7,  // linkD,High prio,Jitter,GMSL2 tx,id = 7
	0x03AE, 0x07,  // linkD,disable GMSL2 rx, id = 7
//MFP4
	0x030D, 0xa7,  // pulldown,push-pull,id = 7
	0x030E, 0x07,  // id = 7
	0x030C, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
	0x0344, 0xe7,  // linkB,High prio,Jitter,GMSL2 tx,id = 7
	0x0345, 0x07,  // linkB,disable GMSL2 rx, id = 7
	0x037A, 0xe7,  // linkC,High prio,Jitter,GMSL2 tx,id = 7
	0x037B, 0x07,  // linkC,disable GMSL2 rx, id = 7
	0x03B1, 0xe7,  // linkD,High prio,Jitter,GMSL2 tx,id = 7
	0x03B2, 0x07,  // linkD,disable GMSL2 rx, id = 7
};

static uint16_t lce_max96712_trigger_setting_mfp[] = {
	//  MFP0
	0x0301, 0xa9,  // pulldown,push-pull,id = 9
	0x0302, 0x09,  // id = 9
	0x0300, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
	0x0337, 0xe9,  // linkB,High prio,Jitter,GMSL2 tx,id = 9
	0x0338, 0x09,  // linkB,disable GMSL2 rx, id = 9
	0x036D, 0xe9,  // linkC,High prio,Jitter,GMSL2 tx,id = 9
	0x036E, 0x09,  // linkC,disable GMSL2 rx, id = 9
	0x03A4, 0xe9,  // linkD,High prio,Jitter,GMSL2 tx,id = 9
	0x03A5, 0x09,  // linkD,disable GMSL2 rx, id = 9
	//  MFP1
	0x0304, 0xa9,  // pulldown,push-pull,id = 9
	0x0305, 0x09,  // id = 9
	0x0303, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
	0x033A, 0xe9,  // linkB,High prio,Jitter,GMSL2 tx,id = 9
	0x033B, 0x09,  // linkB,disable GMSL2 rx, id = 9
	0x0371, 0xe9,  // linkC,High prio,Jitter,GMSL2 tx,id = 9
	0x0372, 0x09,  // linkC,disable GMSL2 rx, id = 9
	0x03A7, 0xe9,  // linkD,High prio,Jitter,GMSL2 tx,id = 9
	0x03A8, 0x09,  // linkD,disable GMSL2 rx, id = 9
	//  MFP2
	0x0307, 0xa9,  // pulldown,push-pull,id = 9
	0x0308, 0x09,  // id = 9
	0x0306, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
	0x033D, 0xe9,  // linkB,High prio,Jitter,GMSL2 tx,id = 9
	0x033E, 0x09,  // linkB,disable GMSL2 rx, id = 9
	0x0374, 0xe9,  // linkC,High prio,Jitter,GMSL2 tx,id = 9
	0x0375, 0x09,  // linkC,disable GMSL2 rx, id = 9
	0x03AA, 0xe9,  // linkD,High prio,Jitter,GMSL2 tx,id = 9
	0x03AB, 0x09,  // linkD,disable GMSL2 rx, id = 9
	//  MFP3
	0x030A, 0xa9,  // pulldown,push-pull,id = 9
	0x030B, 0x09,  // id = 9
	0x0309, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
	0x0341, 0xe9,  // linkB,High prio,Jitter,GMSL2 tx,id = 9
	0x0342, 0x09,  // linkB,disable GMSL2 rx, id = 9
	0x0377, 0xe9,  // linkC,High prio,Jitter,GMSL2 tx,id = 9
	0x0378, 0x09,  // linkC,disable GMSL2 rx, id = 9
	0x03AD, 0xe9,  // linkD,High prio,Jitter,GMSL2 tx,id = 9
	0x03AE, 0x09,  // linkD,disable GMSL2 rx, id = 9
	//  MFP4
	0x030D, 0xa9,  // pulldown,push-pull,id = 9
	0x030E, 0x09,  // id = 9
	0x030C, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
	0x0344, 0xe9,  // linkB,High prio,Jitter,GMSL2 tx,id = 9
	0x0345, 0x09,  // linkB,disable GMSL2 rx, id = 9
	0x037A, 0xe9,  // linkC,High prio,Jitter,GMSL2 tx,id = 9
	0x037B, 0x09,  // linkC,disable GMSL2 rx, id = 9
	0x03B1, 0xe9,  // linkD,High prio,Jitter,GMSL2 tx,id = 9
	0x03B2, 0x09,  // linkD,disable GMSL2 rx, id = 9
};

static uint16_t max96712_trigger_setting_mfp14[] = {
   0x032d, 0xa7,  // pulldown,push-pull,id = 7
   0x032e, 0x07,  // id = 7
   0x032c, 0xeb,  // 1M,High prio,Jitter,output 0,GMSL2 tx
   0x0364, 0xe7,  // linkB,High prio,Jitter,GMSL2 tx,id = 7
   0x0365, 0x07,  // linkB,disable GMSL2 rx, id = 7
   0x039a, 0xe7,  // linkC,High prio,Jitter,GMSL2 tx,id = 7
   0x039b, 0x07,  // linkC,disable GMSL2 rx, id = 7
   0x03d1, 0xe7,  // linkD,High prio,Jitter,GMSL2 tx,id = 7
   0x03d2, 0x07,  // linkD,disable GMSL2 rx, id = 7
};

static uint16_t max9296_start_setting[] = {
	0x0313, 0x62,  	// MIPI output enable
	// 0x0330, 0x84,    // MIPI csi force enable
};

static uint16_t max9296_stop_setting[] = {
	0x0313, 0x00,  	// MIPI output enable
	// 0x0330, 0x04,    // MIPI csi force disenable
};

static uint16_t max96712_tp_start_setting[] = {
	0x08A0, 0x84,  	// MIPI csi force enable
};

static uint16_t max96712_tp_stop_setting[] = {
	0x08A0, 0x04,  	// MIPI csi not force
};

static uint16_t max96712_start_setting[] = {
	0x040B, 0x62,  	// MIPI output enable
	// 0x08A0, 0x84,  	// MIPI csi force enable
};

static uint16_t max96712_stop_setting[] = {
	0x040B, 0x00,  	// MIPI output enable
	// 0x08A0, 0x04,  	// MIPI csi not force
};

static uint8_t max9296_max96717_dual_init_setting[] = {
	0x04, 0x90, 0x00, 0x10, 0xf1,
	0x00, 0xFF,
	0x04, 0x90, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x90, 0x15, 0x49, 0x75,

	0x04, 0x90, 0x00, 0x01, 0x01,
	// Disable MAX9296A MIPI output, CSI_OUT_EN=0
	0x04, 0x90, 0x03, 0x13, 0x00,

// --------------LINK A () MAX96717 Settings----------------------
	0x04, 0x90, 0x00, 0x10, 0x01,
	0x04, 0x90, 0x00, 0x10, 0x21,
	0x00, 0x32,

	// set I2C addr
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x6C,

	0x04, 0x82, 0x00, 0x6B, 0x16,
	0x04, 0x82, 0x00, 0x73, 0x17,
	0x04, 0x82, 0x00, 0x7B, 0x36,
	0x04, 0x82, 0x00, 0x83, 0x36,
	0x04, 0x82, 0x00, 0x93, 0x36,
	0x04, 0x82, 0x00, 0x9B, 0x36,
	0x04, 0x82, 0x00, 0xA3, 0x36,
	0x04, 0x82, 0x00, 0xAB, 0x36,
	0x04, 0x82, 0x00, 0x8B, 0x36,

	0x04, 0x82, 0x02, 0xd3, 0x00,
	0x04, 0x82, 0x00, 0x02, 0x43,
	0x04, 0x82, 0x03, 0x83, 0x00,
	0x04, 0x82, 0x03, 0x18, 0x6C,
	0x04, 0x82, 0x03, 0xf1, 0x09,
	0x04, 0x82, 0x03, 0xf0, 0x51,
	0x04, 0x82, 0x05, 0x70, 0x1C,
	0x04, 0x82, 0x05, 0x70, 0x0C,
	0x04, 0x82, 0x00, 0x06, 0xb1,
	0x04, 0x82, 0x02, 0xbf, 0x60,
	0x04, 0x82, 0x02, 0xbe, 0x90,
	0x04, 0x82, 0x02, 0xd3, 0x90,
	0x04, 0x82, 0x00, 0x5B, 0x02,       // Pipe Z ID = 2
	0x00, 0x32,

// -------------LINK B () MAX967171 Settings-------------------
	0x04, 0x90, 0x00, 0x10, 0x02,
	0x04, 0x90, 0x00, 0x10, 0x22,
	0x00, 0x5F,

	// set I2C addr
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,
	0x00, 0x32,

	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x00, 0x02, 0x43,
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0x18, 0x6C,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x05, 0x70, 0x1C,
	0x04, 0x84, 0x05, 0x70, 0x0C,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xbf, 0x60,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xd3, 0x90,
	0x04, 0x84, 0x00, 0x5B, 0x01,       // Pipe Z ID = 1
	0x00, 0x32,

// --------------Enable LINK A/LINK B------------------------
	0x04, 0x90, 0x00, 0x10, 0x23,
	0x00, 0x5F,

// ------------------ MAX9296 Settings -----------------------
	0x04, 0x90, 0x03, 0x30, 0x04,       // 2x4 mode
	// 0x04, 0x90, 0x03, 0x33, 0x4E,    // Lane Mapping
	// 0x04, 0x90, 0x03, 0x34, 0xE4,    // Lane Mapping

	// Software override for BPP, VC and DT
	// 0x04, 0x90, 0x03, 0x13, 0x60,
	0x04, 0x90, 0x03, 0x16, 0xAC,
	0x04, 0x90, 0x03, 0x17, 0xBC,
	0x04, 0x90, 0x03, 0x18, 0x00,
	0x04, 0x90, 0x03, 0x19, 0x40,
	0x04, 0x90, 0x03, 0x14, 0x11,      // pipeY VC=1
	0x04, 0x90, 0x03, 0x15, 0x00,      // pipeZ VC=0

	0x04, 0x90, 0x04, 0x4A, 0xD0,      // Four lane output from MIPI Port A
	0x04, 0x90, 0x03, 0x20, 0x6C,      // Set MIPI speed 800Mbps, PHY1 soft override
	0x04, 0x90, 0x03, 0x23, 0x6C,      // Set MIPI speed 1200Mbps, PHY2 soft override

	// Send RAW12, FS, and FE from Pipe Y to Controller 1
	0x04, 0x90, 0x04, 0x4B, 0x07,     // Enable 3 Mappings
	0x04, 0x90, 0x04, 0x6D, 0x15,     // Destionation Controller = Controller 1. Controller 1 sends data to MIPI Port A
	// For the following MSB 2 bits = VC, LSB 6 bits =DT
	0x04, 0x90, 0x04, 0x4D, 0x2C,     // SRC  0b00011110, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4E, 0x6C,     // DEST 0b01011110, DT = 0x2C VC=1
	0x04, 0x90, 0x04, 0x4F, 0x00,     // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x50, 0x40,     // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x51, 0x01,     // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x52, 0x41,     // DEST DT = Frame End

	// Send YUV422, FS, and FE from Pipe Z to Controller 1
	0x04, 0x90, 0x04, 0x8B, 0x07,     // Enable 3 Mappings
	0x04, 0x90, 0x04, 0xAD, 0x15,     // Destionation Controller = Controller 1. Controller 2 sends data to MIPI Port A
	// For the following MSB 2 bits = VC, LSB 6 bits = DT
	0x04, 0x90, 0x04, 0x8D, 0x2C,     // SRC  0b00011110, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x8E, 0x2C,     // DEST 0b00011110, DT = 0x2C
	0x04, 0x90, 0x04, 0x8F, 0x00,     // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x90, 0x00,     // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x91, 0x01,     // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x92, 0x01,     // DEST DT = Frame End

	// 0x04, 0x90, 0x00, 0x50, 0x00,  // 9296 pipex (ID0), map to pipeX
	0x04, 0x90, 0x00, 0x51, 0x01,     // 9296 pipeY (ID1), map to pipeY
	0x04, 0x90, 0x00, 0x52, 0x02,     // 9296 pipeZ (ID2), map to pipeZ
	// 0x04, 0x90, 0x00, 0x53, 0x03,  // 9296 pipeU (ID3), map to pipeU

	0x04, 0x90, 0x03, 0x25, 0x80,	  // wait for a new frame
};

static uint8_t max9296_max9295_dual_init_setting[] = {
	0x04, 0x90, 0x00, 0x10, 0xf1,
	0x00, 0xFF,
	0x04, 0x90, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x90, 0x15, 0x49, 0x75,

	// Disable MAX9296A MIPI output, CSI_OUT_EN=0
	0x04, 0x90, 0x03, 0x13, 0x00,

// --------------LINK A () MAX9295A Settings----------------------
	0x04, 0x90, 0x00, 0x10, 0x01,
	0x04, 0x90, 0x00, 0x10, 0x21,
	0x00, 0x32,

	// set I2C addr
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x6C,

	0x04, 0x82, 0x00, 0x6B, 0x16,
	0x04, 0x82, 0x00, 0x73, 0x17,
	0x04, 0x82, 0x00, 0x7B, 0x36,
	0x04, 0x82, 0x00, 0x83, 0x36,
	0x04, 0x82, 0x00, 0x93, 0x36,
	0x04, 0x82, 0x00, 0x9B, 0x36,
	0x04, 0x82, 0x00, 0xA3, 0x36,
	0x04, 0x82, 0x00, 0xAB, 0x36,
	0x04, 0x82, 0x00, 0x8B, 0x36,
	0x00, 0x32,

// -------------LINK B () MAX9295A Settings-------------------
	0x04, 0x90, 0x00, 0x10, 0x02,
	0x04, 0x90, 0x00, 0x10, 0x22,
	0x00, 0x5F,

	// set I2C addr
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,
	0x00, 0x32,

// --------------Enable LINK A/LINK B------------------------
	0x04, 0x90, 0x00, 0x10, 0x23,
	0x00, 0x5F,

	0x04, 0x82, 0x02, 0xbe, 0x00,       // GPIO0 output value 0
	0x04, 0x82, 0x00, 0x02, 0x43,       // enable Video transmit Channel Z
	0x04, 0x82, 0x03, 0x30, 0x00,       // Set SER to 1x4 mode
	0x04, 0x82, 0x03, 0x31, 0x33,       // Set 4 Lanes for SER
	0x04, 0x82, 0x03, 0x32, 0xE0,       // Map mipi data lane PHY1_Lane1->D3,  Lane0->D2
	0x04, 0x82, 0x03, 0x33, 0x04,       // Map mipi data Lane PHY2_Lane1->D1; Lane0->D0
	0x04, 0x82, 0x03, 0x08, 0x64,       // Enable info lines: PORT B && Pipe Z
	0x04, 0x82, 0x03, 0x11, 0x40,       // Start video from Port B && Pipe Z
	//0x04, 0x82, 0x02, 0xd6, 0x90,       // GPIO8 output value 1
	0x04, 0x82, 0x02, 0xbe, 0x18,       // GPIO0 output value 1

	// Set 9295A pipe X stream ID
	0x04, 0x82, 0x03, 0x14, 0x6c,       // Pipe_Z RAW12
	0x04, 0x82, 0x00, 0x5B, 0x12,       // pipe Z ID =2; 9295A pipeZ(2)
	0x00, 0x32,

	0x04, 0x84, 0x02, 0xbe, 0x00,       // GPIO0 output value 0
	0x04, 0x84, 0x00, 0x02, 0x23,       // enable Video transmit Channel Y
	0x04, 0x84, 0x03, 0x30, 0x00,       // Set SER to 1x4 mode
	0x04, 0x84, 0x03, 0x31, 0x33,       // Set 4 Lanes for SER
	0x04, 0x84, 0x03, 0x32, 0xE0,       // Map mipi data lane PHY1_Lane1->D3,  Lane0->D2
	0x04, 0x84, 0x03, 0x33, 0x04,       // Map mipi data Lane PHY2_Lane1->D1; Lane0->D0
	0x04, 0x84, 0x03, 0x08, 0x62,       // Enable info lines: PORT B && Pipe Y
	0x04, 0x84, 0x03, 0x11, 0x20,       // Start video from Port B && Pipe Y
	//0x04, 0x84, 0x02, 0xd6, 0x90,       // GPIO8 output value 1
	0x04, 0x84, 0x02, 0xbe, 0x18,       // GPIO0 output value 1

	// Set 9295A pipe Y stream ID
	0x04, 0x84, 0x03, 0x16, 0x6C,       // Pipe_Y RAW12
	0x04, 0x84, 0x00, 0x57, 0x11,       // Pipe Y ID = 1

// ------------------ MAX9296 Settings -----------------------
	0x04, 0x90, 0x03, 0x30, 0x04,       // 2x4 mode
	// 0x04, 0x90, 0x03, 0x33, 0x4E,    // Lane Mapping
	// 0x04, 0x90, 0x03, 0x34, 0xE4,    // Lane Mapping

	// Software override for BPP, VC and DT
	// 0x04, 0x90, 0x03, 0x13, 0x60,
	0x04, 0x90, 0x03, 0x16, 0xAC,
	0x04, 0x90, 0x03, 0x17, 0xBC,
	0x04, 0x90, 0x03, 0x18, 0x00,
	0x04, 0x90, 0x03, 0x19, 0x40,
	0x04, 0x90, 0x03, 0x14, 0x11,      // pipeY VC=1
	0x04, 0x90, 0x03, 0x15, 0x00,      // pipeZ VC=0

	0x04, 0x90, 0x04, 0x4A, 0xD0,      // Four lane output from MIPI Port A
	0x04, 0x90, 0x03, 0x20, 0x6C,      // Set MIPI speed 800Mbps, PHY1 soft override
	0x04, 0x90, 0x03, 0x23, 0x6C,      // Set MIPI speed 1200Mbps, PHY2 soft override

	// Send RAW12, FS, and FE from Pipe Y to Controller 1
	0x04, 0x90, 0x04, 0x4B, 0x07,     // Enable 3 Mappings
	0x04, 0x90, 0x04, 0x6D, 0x15,     // Destionation Controller = Controller 1. Controller 1 sends data to MIPI Port A
	// For the following MSB 2 bits = VC, LSB 6 bits =DT
	0x04, 0x90, 0x04, 0x4D, 0x2C,     // SRC  0b00011110, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4E, 0x6C,     // DEST 0b01011110, DT = 0x2C VC=1
	0x04, 0x90, 0x04, 0x4F, 0x00,     // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x50, 0x40,     // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x51, 0x01,     // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x52, 0x41,     // DEST DT = Frame End

	// Send YUV422, FS, and FE from Pipe Z to Controller 1
	0x04, 0x90, 0x04, 0x8B, 0x07,     // Enable 3 Mappings
	0x04, 0x90, 0x04, 0xAD, 0x15,     // Destionation Controller = Controller 1. Controller 2 sends data to MIPI Port A
	// For the following MSB 2 bits = VC, LSB 6 bits = DT
	0x04, 0x90, 0x04, 0x8D, 0x2C,     // SRC  0b00011110, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x8E, 0x2C,     // DEST 0b00011110, DT = 0x2C
	0x04, 0x90, 0x04, 0x8F, 0x00,     // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x90, 0x00,     // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x91, 0x01,     // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x92, 0x01,     // DEST DT = Frame End

	// 0x04, 0x90, 0x00, 0x50, 0x00,  // 9296 pipex (ID0), map to pipeX
	0x04, 0x90, 0x00, 0x51, 0x01,     // 9296 pipeY (ID1), map to pipeY
	0x04, 0x90, 0x00, 0x52, 0x02,     // 9296 pipeZ (ID2), map to pipeZ
	// 0x04, 0x90, 0x00, 0x53, 0x03,  // 9296 pipeU (ID3), map to pipeU

	0x04, 0x90, 0x03, 0x25, 0x80,	  // wait for a new frame
};

/* weisen0820 + sensingx3c -> max9296: A+B */
uint8_t weisen_max9296_max9295_dual_init_setting[] = {
	// reset 0820
	0x04, 0x90, 0x00, 0x10, 0xf1,
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x90, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x90, 0x15, 0x49, 0x75,


	// LINKA: MAX9295 - i2c.
	0x04, 0x90, 0x00, 0x10, 0x01,
	0x04, 0x90, 0x00, 0x10, 0x21,
	0x00, 0x32,

	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x32,
	0x04, 0x82, 0x00, 0x45, 0x30,

	// split mode.
	0x04, 0x82, 0x00, 0x6B, 0x16,
	0x04, 0x82, 0x00, 0x73, 0x17,
	0x04, 0x82, 0x00, 0x7B, 0x36,
	0x04, 0x82, 0x00, 0x83, 0x36,
	0x04, 0x82, 0x00, 0x93, 0x36,
	0x04, 0x82, 0x00, 0x9B, 0x36,
	0x04, 0x82, 0x00, 0xA3, 0x36,
	0x04, 0x82, 0x00, 0xAB, 0x36,
	0x04, 0x82, 0x00, 0x8B, 0x36,
	0x00, 0x32,

	// LINKB: MAX9295 - i2c.
	0x04, 0x90, 0x00, 0x10, 0x02,
	0x04, 0x90, 0x00, 0x10, 0x22,
	0x00, 0x32,

	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	// LINKA + LINKB: MAX9295A config.
	0x04, 0x90, 0x00, 0x10, 0x23,
	0x00, 0x5F,

	// LinkA: MAX9295 - Serializer config
	0x04, 0x82, 0x00, 0x10, 0x15,
	0x04, 0x82, 0x00, 0x12, 0x14,
	0x04, 0x82, 0x03, 0x11, 0x40,	 // start x/y/z/u from B,40
	0x04, 0x82, 0x03, 0x08, 0x64,	 // x/y/z/u selected B,64
	0x04, 0x82, 0x00, 0x02, 0x43,	 // Video transmit enable  //transmit Z,43

	0x04, 0x82, 0x03, 0x18, 0x6c,

	0x04, 0x82, 0x02, 0xD6, 0x80,
	0x00, 0x20,
	0x04, 0x82, 0x02, 0xD6, 0x9C,

	// LinkB: MAX9295 - Serializer config
	0x04, 0x84, 0x02, 0xbe, 0x00,       // GPIO0 output value 0
	0x04, 0x84, 0x00, 0x02, 0x23,       // enable Video transmit Channel Y
	0x04, 0x84, 0x03, 0x30, 0x00,       // Set SER to 1x4 mode
	0x04, 0x84, 0x03, 0x31, 0x33,       // Set 4 Lanes for SER
	0x04, 0x84, 0x03, 0x32, 0xE0,       // Map mipi data lane PHY1_Lane1->D3,  Lane0->D2
	0x04, 0x84, 0x03, 0x33, 0x04,       // Map mipi data Lane PHY2_Lane1->D1; Lane0->D0
	0x04, 0x84, 0x03, 0x08, 0x62,       // Enable info lines: PORT B && Pipe Y
	0x04, 0x84, 0x03, 0x11, 0x20,       // Start video from Port B && Pipe Y
	//0x04, 0x84, 0x02, 0xd6, 0x90,       // GPIO8 output value 1
	0x04, 0x84, 0x02, 0xbe, 0x18,       // GPIO0 output value 1

	// Set 9295A pipe Y stream ID
	0x04, 0x84, 0x03, 0x16, 0x6C,       // Pipe_Y RAW12
	0x04, 0x84, 0x00, 0x57, 0x11,       // Pipe Y ID = 1

	// MAX9296 - Deserializer config
	0x04, 0x90, 0x03, 0x13, 0x00,
	0x04, 0x90, 0x03, 0x16, 0x80,	// y dt: 0x2c (x dt: 0x00)
	0x04, 0x90, 0x03, 0x17, 0xBC,	// z dt: 0x2c
	0x04, 0x90, 0x03, 0x18, 0x00,	// (u dt: 0x00)
	0x04, 0x90, 0x03, 0x19, 0x6C,	// y z dt: 12
	0x04, 0x90, 0x03, 0x1A, 0x00,
	0x04, 0x90, 0x03, 0x14, 0x10,	// y: vc1
	0x04, 0x90, 0x03, 0x15, 0x00,   // z: vc0

	0x04, 0x90, 0x03, 0x1D, 0xAC, 	// y: soft override.
	0x04, 0x90, 0x03, 0x20, 0x79, 	// z: soft overfide, Port A 2.5G
	0x04, 0x90, 0x03, 0x23, 0x39,   // PortB: 2.5G

	// y map to vc1 of PortA.
	0x04, 0x90, 0x04, 0x4B, 0x07,   // Enable 3 Mappings
	0x04, 0x90, 0x04, 0x6D, 0x15,   // Destionation Controller = Controller 1. Controller 1 sends data to MIPI Port A
	// For the following MSB 2 bits = VC, LSB 6 bits =DT
	0x04, 0x90, 0x04, 0x4D, 0x2C,   // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4E, 0x6C,   // DEST 0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4F, 0x00,   // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x50, 0x40,   // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x51, 0x01,   // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x52, 0x41,   // DEST DT = Frame End

	// z map to vc0 of PortA.
	0x04, 0x90, 0x04, 0x8B, 0x07,     // Enable 3 Mappings
	0x04, 0x90, 0x04, 0xAD, 0x15,     // Destionation Controller = Controller 1. Controller 2 sends data to MIPI Port A
	// For the following MSB 2 bits = VC, LSB 6 bits = DT
	0x04, 0x90, 0x04, 0x8D, 0x2C,     // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x8E, 0x2C,     // DEST 0b01101100, DT = 0x2C VC=1
	0x04, 0x90, 0x04, 0x8F, 0x00,     // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x90, 0x00,     // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x91, 0x01,     // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x92, 0x01,     // DEST DT = Frame End

	0x04, 0x90, 0x03, 0x25, 0x80,
};

uint8_t max96718_reset_serial_with_3G_init[] = {
	0x04, 0x90, 0x00, 0x10, 0xf3,
	0x00, 0xff,
	0x00, 0xff,
	// LINKA + LINKB: MAX96717+MAX96717F config.
	0x04, 0x90, 0x00, 0x04, 0x01,       // 96717F:GMSL2 LinkB 3Gbps
	0x04, 0x90, 0x00, 0x12, 0x24,       // reset oneshot LINKB
	0x04, 0x90, 0x00, 0x10, 0x23,       // choose LINKA+LINKB and rest LINKA
	0x00, 0x5F,
};

uint8_t max96718_reset_serial_with_3G_linka_init[] = {
	0x04, 0x90, 0x00, 0x10, 0xf3,
	0x00, 0xff,
	0x00, 0xff,
	// LINKA + LINKB: MAX96717+MAX96717F config.
	0x04, 0x50, 0x00, 0x01, 0x01,  // LinkA:GMSL2 LINKA 3Gbps
	0x04, 0x50, 0x00, 0x10, 0x23,  // choose LINKA+LINKB and rest LINKA
	0x00, 0x5F,
};

/* ovx8b + ovx3c -> max96718 */
uint8_t sunny_max96718_max96717_max96717_init_setting[] = {
#ifndef POC_RETRY_POLICY
	0x03, 0x52, 0x01, 0x00,
	0x00, 0xff,
	0x03, 0x52, 0x01, 0x1f,
	0x00, 0xff,
#endif
	0x04, 0x90, 0x00, 0x10, 0xf3,
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x90, 0x14, 0x49, 0xF5,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x90, 0x15, 0x49, 0xF5,

	0x04, 0x90, 0x00, 0x04, 0x01,       // 96717:GMSL2 3Gbps
	0x04, 0x90, 0x00, 0x12, 0x24,       // reset LINKB
	0x04, 0x90, 0x00, 0x10, 0x23,       // choose LINKA+LINKB and rest LINKA
	0x00, 0x32,

	// open LINKA and close LINKB: MAX9295 - i2c.
	0x04, 0x90, 0x00, 0x01, 0x02,
	0x04, 0x90, 0x00, 0x03, 0x57,
	0x00, 0x32,

	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xA2,
	0x04, 0x82, 0x00, 0x43, 0xA0,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x20,

	// split mode.
	0x04, 0x82, 0x00, 0x6B, 0x16,
	0x04, 0x82, 0x00, 0x73, 0x17,
	0x04, 0x82, 0x00, 0x7B, 0x36,
	0x04, 0x82, 0x00, 0x83, 0x36,
	0x04, 0x82, 0x00, 0x93, 0x36,
	0x04, 0x82, 0x00, 0x9B, 0x36,
	0x04, 0x82, 0x00, 0xA3, 0x36,
	0x04, 0x82, 0x00, 0xAB, 0x36,
	0x04, 0x82, 0x00, 0x8B, 0x36,
	0x00, 0x32,

	// open LINKB close LINKA: MAX96717 - i2c.
	0x04, 0x90, 0x00, 0x01, 0x12,       // close LINKA
	0x04, 0x90, 0x00, 0x03, 0x53,       // open LINKB
	0x00, 0x32,

	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xA4,
	0x04, 0x84, 0x00, 0x43, 0xA0,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6c,

	// LINKA + LINKB: MAX9295A+MAX96717 config.
	0x04, 0x90, 0x00, 0x01, 0x02,
	0x04, 0x90, 0x00, 0x03, 0x53,
	0x00, 0x5F,

	// MAX96717 - Serializer config
	0x04, 0x82, 0x02, 0xd3, 0x00,
	0x04, 0x82, 0x00, 0x02, 0x43,
	0x04, 0x82, 0x03, 0x83, 0x00,
	0x04, 0x82, 0x03, 0x18, 0x6C,
	0x04, 0x82, 0x03, 0xf1, 0x09,
	0x04, 0x82, 0x03, 0xf0, 0x51,
	0x04, 0x82, 0x05, 0x70, 0x1C,
	0x04, 0x82, 0x05, 0x70, 0x0C,
	0x04, 0x82, 0x00, 0x06, 0xb1,
	0x04, 0x82, 0x02, 0xbf, 0x60,
	0x04, 0x82, 0x02, 0xbe, 0x90,
	0x04, 0x82, 0x02, 0xd3, 0x90,
	0x04, 0x82, 0x00, 0x5B, 0x01,       // Pipe Z ID = 1
	0x00, 0x32,

	// MAX96717 - Serializer config
	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x00, 0x02, 0x43,
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0x18, 0x6C,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x05, 0x70, 0x1C,
	0x04, 0x84, 0x05, 0x70, 0x0C,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xbf, 0x60,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xd3, 0x90,
	// 0x04, 0x84, 0x00, 0x5B, 0x01,       // Pipe Z ID = 1
	0x00, 0x32,

	// MAX9296 - Deserializer config
	0x04, 0x90, 0x03, 0x13, 0x00,
	0x04, 0x90, 0x03, 0x30, 0x04,   // 2*4 PORTA(PHY0+PHY1) PORTB(PHY2+PHY3)
	0x04, 0x90, 0x03, 0x16, 0x80, 	// y dt: 0x2c (x dt: 0x00)
	0x04, 0x90, 0x03, 0x17, 0xBC, 	// z dt: 0x2c
	0x04, 0x90, 0x03, 0x18, 0x00, 	// (u dt: 0x00)
	0x04, 0x90, 0x03, 0x19, 0x6C, 	// y z dt: 12
	0x04, 0x90, 0x03, 0x1A, 0x00,
	0x04, 0x90, 0x03, 0x14, 0x10, 	// y: vc1
	0x04, 0x90, 0x03, 0x15, 0x00,   // z: vc0

	// 0x04, 0x90, 0x03, 0x1D, 0xAC, 	// y: soft override.
	// 0x04, 0x90, 0x03, 0x20, 0x79, 	// z: soft overfide, Port A 2.5G
	// 0x04, 0x90, 0x03, 0x23, 0x39,   // PortB: 2.5G

	// y map to vc1 of PortA.
	0x04, 0x90, 0x04, 0x4B, 0x07,    // Enable 3 Mappings
	// 0x04, 0x50, 0x04, 0x6D, 0x2a,    // Destionation Controller = Controller 1. Controller 1 sends data to MIPI Port A
	// 0x04, 0x90, 0x04, 0x6D, 0x15,
	// For the following MSB 2 bits = VC, LSB 6 bits =DT
	0x04, 0x90, 0x04, 0x4D, 0x2C,    // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4E, 0x6C,    // DEST 0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4F, 0x00,    // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x50, 0x40,    // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x51, 0x01,    // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x52, 0x41,    // DEST DT = Frame End

	// z map to vc0 of PortA.
	0x04, 0x90, 0x04, 0x8B, 0x07,    // Enable 3 Mappings
	// 0x04, 0x50, 0x04, 0xAD, 0x2a, // Destionation Controller = Controller 1. Controller 2 sends data to MIPI Port A
	// 0x04, 0x90, 0x04, 0xAD, 0x15,
	// For the following MSB 2 bits = VC, LSB 6 bits = DT
	0x04, 0x90, 0x04, 0x8D, 0x2C,    // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x8E, 0x2C,    // DEST 0b01101100, DT = 0x2C VC=1
	0x04, 0x90, 0x04, 0x8F, 0x00,    // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x90, 0x00,    // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x91, 0x01,    // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x92, 0x01,    // DEST DT = Frame End

	0x04, 0x90, 0x03, 0x25, 0x80,
	0x04, 0x90, 0x03, 0x13, 0x02,    // MIPI output enable
};

/* ovx8b + ovx3c -> max9296 */
uint8_t sunny_max9296_max96717_max96717_init_setting[] = {
#ifndef POC_RETRY_POLICY
	0x03, 0x50, 0x01, 0x00,
	0x00, 0xff,
	0x03, 0x50, 0x01, 0x1f,
	0x00, 0xff,
#endif
	0x04, 0x90, 0x00, 0x10, 0xf1,
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x90, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x90, 0x15, 0x49, 0x75,

	0x04, 0x80, 0x00, 0x01, 0x04,  // 9295: GMSL2 3Gbps.
	0x04, 0x90, 0x00, 0x01, 0x01,  // 9296: GMSL2 3Gbps.
	0x00, 0xff,

	// LINKA: MAX9295 - i2c.
	0x04, 0x90, 0x00, 0x10, 0x01,
	0x04, 0x90, 0x00, 0x10, 0x21,
	0x00, 0x32,

	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xA2,
	0x04, 0x82, 0x00, 0x43, 0xA0,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x20,

	// split mode.
	0x04, 0x82, 0x00, 0x6B, 0x16,
	0x04, 0x82, 0x00, 0x73, 0x17,
	0x04, 0x82, 0x00, 0x7B, 0x36,
	0x04, 0x82, 0x00, 0x83, 0x36,
	0x04, 0x82, 0x00, 0x93, 0x36,
	0x04, 0x82, 0x00, 0x9B, 0x36,
	0x04, 0x82, 0x00, 0xA3, 0x36,
	0x04, 0x82, 0x00, 0xAB, 0x36,
	0x04, 0x82, 0x00, 0x8B, 0x36,
	0x00, 0x32,

	// LINKB: MAX96717 - i2c.
	0x04, 0x90, 0x00, 0x10, 0x22,
	0x00, 0x32,

	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xA4,
	0x04, 0x84, 0x00, 0x43, 0xA0,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	// LINKA + LINKB: MAX96717+MAX96717 config.
	0x04, 0x90, 0x00, 0x10, 0x23,
	0x00, 0x5F,

	// MAX96717 - Serializer config
	0x04, 0x82, 0x02, 0xd3, 0x00,
	0x04, 0x82, 0x00, 0x02, 0x43,
	0x04, 0x82, 0x03, 0x83, 0x00,
	0x04, 0x82, 0x03, 0x18, 0x6C,
	0x04, 0x82, 0x03, 0xf1, 0x09,
	0x04, 0x82, 0x03, 0xf0, 0x51,
	0x04, 0x82, 0x05, 0x70, 0x1C,
	0x04, 0x82, 0x05, 0x70, 0x0C,
	0x04, 0x82, 0x00, 0x06, 0xb1,
	0x04, 0x82, 0x02, 0xbf, 0x60,
	0x04, 0x82, 0x02, 0xbe, 0x90,
	0x04, 0x82, 0x02, 0xd3, 0x90,
	0x04, 0x82, 0x00, 0x5B, 0x01,       // Pipe Z ID = 1
	0x00, 0x32,

	// MAX96717 - Serializer config
	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x00, 0x02, 0x43,
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0x18, 0x6C,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x05, 0x70, 0x1C,
	0x04, 0x84, 0x05, 0x70, 0x0C,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xbf, 0x60,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xd3, 0x90,
	// 0x04, 0x84, 0x00, 0x5B, 0x01,       // Pipe Z ID = 1
	0x00, 0x32,

	// MAX9296 - Deserializer config
	0x04, 0x90, 0x03, 0x13, 0x00,
	0x04, 0x90, 0x03, 0x30, 0x04,   // 2*4 PORTA(PHY0+PHY1) PORTB(PHY2+PHY3)
	0x04, 0x90, 0x03, 0x16, 0x80, 	// y dt: 0x2c (x dt: 0x00)
	0x04, 0x90, 0x03, 0x17, 0xBC, 	// z dt: 0x2c
	0x04, 0x90, 0x03, 0x18, 0x00, 	// (u dt: 0x00)
	0x04, 0x90, 0x03, 0x19, 0x6C, 	// y z dt: 12
	0x04, 0x90, 0x03, 0x1A, 0x00,
	0x04, 0x90, 0x03, 0x14, 0x10, 	// y: vc1
	0x04, 0x90, 0x03, 0x15, 0x00,   // z: vc0
	0x04, 0x90, 0x03, 0x1D, 0xAC, 	// y: soft override.
	0x04, 0x90, 0x03, 0x20, 0x79, 	// z: soft overfide, Port A 2.5G
	0x04, 0x90, 0x03, 0x23, 0x39,   // PortB: 2.5G

	// y map to vc1 of PortA.
	0x04, 0x90, 0x04, 0x4B, 0x07,    // Enable 3 Mappings
	// 0x04, 0x50, 0x04, 0x6D, 0x2a,    // Destionation Controller = Controller 1. Controller 1 sends data to MIPI Port A
	0x04, 0x90, 0x04, 0x6D, 0x15,
	// For the following MSB 2 bits = VC, LSB 6 bits =DT
	0x04, 0x90, 0x04, 0x4D, 0x2C,    // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4E, 0x6C,    // DEST 0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4F, 0x00,    // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x50, 0x40,    // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x51, 0x01,    // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x52, 0x41,    // DEST DT = Frame End

	// z map to vc0 of PortA.
	0x04, 0x90, 0x04, 0x8B, 0x07,    // Enable 3 Mappings
	// 0x04, 0x50, 0x04, 0xAD, 0x2a, // Destionation Controller = Controller 1. Controller 2 sends data to MIPI Port A
	0x04, 0x90, 0x04, 0xAD, 0x15,
	// For the following MSB 2 bits = VC, LSB 6 bits = DT
	0x04, 0x90, 0x04, 0x8D, 0x2C,    // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x8E, 0x2C,    // DEST 0b01101100, DT = 0x2C VC=1
	0x04, 0x90, 0x04, 0x8F, 0x00,    // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x90, 0x00,    // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x91, 0x01,    // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x92, 0x01,    // DEST DT = Frame End

	0x04, 0x90, 0x03, 0x25, 0x80,
	// 0x04, 0x90, 0x03, 0x13, 0x02,    // MIPI output enable
};

/* sensing0820 + sensingx3c -> max9296: A+B */
uint8_t sensing_max9296_max9295_dual_init_setting[] = {
	// reset 0820
	0x04, 0x90, 0x00, 0x10, 0xf1,
	0x00, 0xff,
	0x00, 0xff,

	0x04, 0x90, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x90, 0x15, 0x49, 0x75,

	// LINKA: MAX9295 - i2c.
	0x04, 0x90, 0x00, 0x10, 0x01,
	0x04, 0x90, 0x00, 0x10, 0x21,
	0x00, 0x32,

	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x20,

	// split mode.
	0x04, 0x82, 0x00, 0x6B, 0x16,
	0x04, 0x82, 0x00, 0x73, 0x17,
	0x04, 0x82, 0x00, 0x7B, 0x36,
	0x04, 0x82, 0x00, 0x83, 0x36,
	0x04, 0x82, 0x00, 0x93, 0x36,
	0x04, 0x82, 0x00, 0x9B, 0x36,
	0x04, 0x82, 0x00, 0xA3, 0x36,
	0x04, 0x82, 0x00, 0xAB, 0x36,
	0x04, 0x82, 0x00, 0x8B, 0x36,
	0x00, 0x32,

	// LINKB: MAX9295 - i2c.
	0x04, 0x90, 0x00, 0x10, 0x02,
	0x04, 0x90, 0x00, 0x10, 0x22,
	0x00, 0x32,

	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	// LINKA + LINKB: MAX9295A config.
	0x04, 0x90, 0x00, 0x10, 0x23,
	0x00, 0x5F,

	0x04, 0x82, 0x03, 0x11, 0x20,	 // start x/y/z/u from B,20
	0x04, 0x82, 0x03, 0x08, 0x62,	 // x/y/z/u selected B,62
	0x04, 0x82, 0x00, 0x02, 0x23,	 // Video transmit enable  //transmit Y,23

	0x04, 0x82, 0x03, 0x16, 0x6c,

	0x04, 0x82, 0x03, 0xf0, 0x51,
	0x04, 0x82, 0x00, 0x03, 0x03,
	0x04, 0x82, 0x00, 0x06, 0xb1,
	0x04, 0x82, 0x02, 0xbe, 0x18,
	0x04, 0x82, 0x02, 0xbf, 0x60,
	0x04, 0x82, 0x00, 0x57, 0x02,    // Pipe Y ID = 2

	0x04, 0x84, 0x02, 0xbe, 0x00,       // GPIO0 output value 0
	0x04, 0x84, 0x00, 0x02, 0x23,       // enable Video transmit Channel Y
	0x04, 0x84, 0x03, 0x30, 0x00,       // Set SER to 1x4 mode
	0x04, 0x84, 0x03, 0x31, 0x33,       // Set 4 Lanes for SER
	0x04, 0x84, 0x03, 0x32, 0xE0,       // Map mipi data lane PHY1_Lane1->D3,  Lane0->D2
	0x04, 0x84, 0x03, 0x33, 0x04,       // Map mipi data Lane PHY2_Lane1->D1; Lane0->D0
	0x04, 0x84, 0x03, 0x08, 0x62,       // Enable info lines: PORT B && Pipe Y
	0x04, 0x84, 0x03, 0x11, 0x20,       // Start video from Port B && Pipe Y
	//0x04, 0x84, 0x02, 0xd6, 0x90,       // GPIO8 output value 1
	0x04, 0x84, 0x02, 0xbe, 0x18,       // GPIO0 output value 1

	// Set 9295A pipe Y stream ID
	0x04, 0x84, 0x03, 0x16, 0x6C,       // Pipe_Y RAW12
	0x04, 0x84, 0x00, 0x57, 0x11,       // Pipe Y ID = 1

	// MAX9296 - Deserializer config
	0x04, 0x90, 0x03, 0x13, 0x00,
	0x04, 0x90, 0x03, 0x16, 0x80,	// y dt: 0x2c (x dt: 0x00)
	0x04, 0x90, 0x03, 0x17, 0xBC,	// z dt: 0x2c
	0x04, 0x90, 0x03, 0x18, 0x00,	// (u dt: 0x00)
	0x04, 0x90, 0x03, 0x19, 0x6C,	// y z dt: 12
	0x04, 0x90, 0x03, 0x1A, 0x00,
	0x04, 0x90, 0x03, 0x14, 0x10,	// y: vc1
	0x04, 0x90, 0x03, 0x15, 0x00,   // z: vc0

	0x04, 0x90, 0x03, 0x1D, 0xAC, 	// y: soft override.
	0x04, 0x90, 0x03, 0x20, 0x79, 	// z: soft overfide, Port A 2.5G
	0x04, 0x90, 0x03, 0x23, 0x39,   // PortB: 2.5G

	// y map to vc1 of PortA.
	0x04, 0x90, 0x04, 0x4B, 0x07,   // Enable 3 Mappings
	0x04, 0x90, 0x04, 0x6D, 0x15,   // Destionation Controller = Controller 1. Controller 1 sends data to MIPI Port A
	// For the following MSB 2 bits = VC, LSB 6 bits =DT
	0x04, 0x90, 0x04, 0x4D, 0x2C,   // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4E, 0x6C,   // DEST 0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4F, 0x00,   // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x50, 0x40,   // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x51, 0x01,   // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x52, 0x41,   // DEST DT = Frame End

	// z map to vc0 of PortA.
	0x04, 0x90, 0x04, 0x8B, 0x07,     // Enable 3 Mappings
	0x04, 0x90, 0x04, 0xAD, 0x15,     // Destionation Controller = Controller 1. Controller 2 sends data to MIPI Port A
	// For the following MSB 2 bits = VC, LSB 6 bits = DT
	0x04, 0x90, 0x04, 0x8D, 0x2C,     // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x8E, 0x2C,     // DEST 0b01101100, DT = 0x2C VC=1
	0x04, 0x90, 0x04, 0x8F, 0x00,     // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x90, 0x00,     // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x91, 0x01,     // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x92, 0x01,     // DEST DT = Frame End

	0x04, 0x90, 0x03, 0x25, 0x80,
};

// #define PATTERN_96712_1G
// #define PATTERN_96712_25fps
static uint8_t max96712_testpattern_quad_init_setting[] = {
	0x04, 0x52, 0x00, 0x13, 0x75,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	// H WANG JAN 2018
	// PG1, 150MHz PCLK, 4k@15fps video patterns (RAW12, 12bpp), x4 aggregated on port A 1x4 @ 2.4Gbps/lane

	// COLOR GRADIENT SETUP - PATGEN MODE = 2,,
	// Set VTG mode VRX_Patgen 0, Generate VS, HS, DE", Invert the VS
	0x04, 0x52, 0x10, 0x50, 0xF3,
	// Set Patgen mode = 2 (Color Gradient), Grad Mode = 0",,
	0x04, 0x52, 0x10, 0x51, 0x10,

	// Set VS_DLY = 0
	0x04, 0x52, 0x10, 0x52, 0x00,
	0x04, 0x52, 0x10, 0x53, 0x00,
	0x04, 0x52, 0x10, 0x54, 0x00,
	// Set VS High  -- 293us
	0x04, 0x52, 0x10, 0x55, 0x00,
	0x04, 0x52, 0x10, 0x56, 0xAB,
	0x04, 0x52, 0x10, 0x57, 0xE0,
#ifdef PATTERN_96712_25fps
	// Set VS Low   -- 39.71ms
	0x04, 0x52, 0x10, 0x58, 0x5A,
	0x04, 0x52, 0x10, 0x59, 0xE1,
	0x04, 0x52, 0x10, 0x5A, 0xA0,
#else
	// Set VS Low   -- 33.0ms
	0x04, 0x52, 0x10, 0x58, 0x4B,
	0x04, 0x52, 0x10, 0x59, 0x9F,
	0x04, 0x52, 0x10, 0x5A, 0x60,
#endif
	// Set HS Delay V2H -- 2.052ms
	0x04, 0x52, 0x10, 0x5B, 0x04,
	0x04, 0x52, 0x10, 0x5C, 0xB2,
	0x04, 0x52, 0x10, 0x5D, 0xB4,
	// Set HS_HIGH  -- 2280
	0x04, 0x52, 0x10, 0x5E, 0x08,
	0x04, 0x52, 0x10, 0x5F, 0xE7,
#ifdef PATTERN_96712_25fps
	// Set HS_LOW   -- 1920
	0x04, 0x52, 0x10, 0x60, 0x07,
	0x04, 0x52, 0x10, 0x61, 0x80,
#else
	// Set HS_LOW   -- 87
	0x04, 0x52, 0x10, 0x60, 0x00,
	0x04, 0x52, 0x10, 0x61, 0x57,
#endif
#ifdef PATTERN_96712_25fps
	// Set HS_CNT   -- 1355
	0x04, 0x52, 0x10, 0x62, 0x05,
	0x04, 0x52, 0x10, 0x63, 0x4B,
#else
	// Set HS_CNT   -- 1982
	0x04, 0x52, 0x10, 0x62, 0x07,
	0x04, 0x52, 0x10, 0x63, 0xBE,
#endif
	// Set DE Delay -- 2.053ms
	0x04, 0x52, 0x10, 0x64, 0x04,
	0x04, 0x52, 0x10, 0x65, 0xB3,
	0x04, 0x52, 0x10, 0x66, 0x20,
	// Set DE_HIGH	-- width: 2048
	0x04, 0x52, 0x10, 0x67, 0x08,
	0x04, 0x52, 0x10, 0x68, 0x00,
#ifdef PATTERN_96712_25fps
	// Set DE_LOW   -- 2152
	0x04, 0x52, 0x10, 0x69, 0x08,
	0x04, 0x52, 0x10, 0x6A, 0x68,
#else
	// Set DE_LOW   -- 319
	0x04, 0x52, 0x10, 0x69, 0x01,
	0x04, 0x52, 0x10, 0x6A, 0x3F,
#endif
	// Set DE_CNT	-- height: 1280
	0x04, 0x52, 0x10, 0x6B, 0x05,
	0x04, 0x52, 0x10, 0x6C, 0x00,

	// Set Grad_INCR_0_0,,
	0x04, 0x52, 0x10, 0x6D, 0x03,

	// CHECKERBOARD SETUP - PATGEN MODE = 1,,
	// Set CHKR_COLOR_A_L_0,,
	0x04, 0x52, 0x10, 0x6E, 0x80,
	// Set CHKR_COLOR_A_M_0,,
	0x04, 0x52, 0x10, 0x6F, 0x00,
	// Set CHKR_COLOR_A_H_0,,
	0x04, 0x52, 0x10, 0x70, 0x04,
	// Set CHKR_COLOR_B_L_0,,
	0x04, 0x52, 0x10, 0x71, 0x00,
	// Set CHKR_COLOR_B_M_0,,
	0x04, 0x52, 0x10, 0x72, 0x08,
	// Set CHKR_COLOR_B_H_0,,
	0x04, 0x52, 0x10, 0x73, 0x80,
	// Set CHKR_RPT_A_0,,
	0x04, 0x52, 0x10, 0x74, 0x50,
	// Set CHKR_RPT_B_0,,
	0x04, 0x52, 0x10, 0x75, 0xA0,
	// Set CHKR_ALT_0,,
	0x04, 0x52, 0x10, 0x76, 0x50,

	// Set Patgen Clk frequency 150MHz
	0x04, 0x52, 0x00, 0x09, 0x02,
	0x04, 0x52, 0x01, 0xDC, 0x00,
	0x04, 0x52, 0x01, 0xFC, 0x00,
	0x04, 0x52, 0x02, 0x1C, 0x00,
	0x04, 0x52, 0x02, 0x3C, 0x00,

	// RAW12 Software override VC/DT/BPP for Pipe 1,2,3 and 4;
	// 0x24 = 6'b100100, 24 = 5'b11000; 0x2C = 6'b101100, 12 = 5'b01100
	// BPP override for 1
	// 0x04, 0x52, 0x04, 0x0B, 0xC2
	0x04, 0x52, 0x04, 0x0B, 0x62,
	// VC override for 1/2/3/4
	0x04, 0x52, 0x04, 0x0C, 0x00,
	0x04, 0x52, 0x04, 0x0D, 0x00,
	// DT override for 1/2/3/4
	// 0x04, 0x52, 0x04, 0x0E, 0xA4
	// 0x04, 0x52, 0x04, 0x0F, 0x94
	// 0x04, 0x52, 0x04, 0x10, 0x90
	0x04, 0x52, 0x04, 0x0E, 0xAC,
	0x04, 0x52, 0x04, 0x0F, 0xBC,
	0x04, 0x52, 0x04, 0x10, 0xB0,
	// BPP override for 2/3/4
	// 0x04, 0x52, 0x04, 0x11, 0xD8
	// 0x04, 0x52, 0x04, 0x12, 0x60
	0x04, 0x52, 0x04, 0x11, 0x6C,
	0x04, 0x52, 0x04, 0x12, 0x30,
	//


	// ----------Deserializer Setup------------
	// Disable GMSL link
	0x04, 0x52, 0x00, 0x06, 0x00,
#ifdef PATTERN_96712_1G
	// Set 1000M DPLL frequency, Enable the software override for 1/2/3/4
	0x04, 0x52, 0x04, 0x15, 0xEA,
	0x04, 0x52, 0x04, 0x18, 0xEA,
	0x04, 0x52, 0x04, 0x1B, 0xEA,
	0x04, 0x52, 0x04, 0x1E, 0xEA,
#else
	// Set 2000M DPLL frequency, Enable the software override for 1/2/3/4
	0x04, 0x52, 0x04, 0x15, 0xF4,
	0x04, 0x52, 0x04, 0x18, 0xF4,
	0x04, 0x52, 0x04, 0x1B, 0xF4,
	0x04, 0x52, 0x04, 0x1E, 0xF4,
#endif
	// Set Alternate Crossbar for Video Pipes 0-3 - REMOVE ALTERNATE CROSSBAR???,,
	// 0x52, 0x1DD, 0x1B
	// 0x52, 0x1FD, 0x1B
	// 0x52, 0x21D, 0x1B
	// 0x52, 0x23D, 0x1B
	// Set Line Start, Line End for Video Pipe 0-3 (Backtop //1-4)",,
	// 0x04, 0x52, 0x04, 0x09, 0x0F
	// Set Lane Count - 4 for script  (CSI_NUM_LANES), DPHY ONLY",,
	0x04, 0x52, 0x09, 0x0A, 0xC0,
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,
	// Set Phy lane Map for all MIPI PHYs,,
	0x04, 0x52, 0x08, 0xA3, 0xE4,
	0x04, 0x52, 0x08, 0xA4, 0xE4,



	// Set MAP_EN_L_0 for map 0
	0x04, 0x52, 0x09, 0x0B, 0x07,
	// Set MAP_DPHY_DEST TO CTRL 1
	0x04, 0x52, 0x09, 0x2D, 0x15,
	// Set MAP_SRC AND DEST for data and FE/FS; [7:6]=VC, [5:0]=DT,,
	// 0x04, 0x52, 0x09, 0x0D, 0x24
	// 0x04, 0x52, 0x09, 0x0E, 0x24
	0x04, 0x52, 0x09, 0x0D, 0x2C,
	0x04, 0x52, 0x09, 0x0E, 0x2C,
	0x04, 0x52, 0x09, 0x0F, 0x00,
	0x04, 0x52, 0x09, 0x10, 0x00,
	0x04, 0x52, 0x09, 0x11, 0x01,
	0x04, 0x52, 0x09, 0x12, 0x01,

	// Set MAP_EN_L_1 for map 1
	0x04, 0x52, 0x09, 0x4B, 0x07,
	// Set MAP_DPHY_DEST TO CTRL 1
	0x04, 0x52, 0x09, 0x6D, 0x15,
	// Set MAP_SRC AND DEST for data and FE/FS; [7:6]=VC, [5:0]=DT,,
	// 0x04, 0x52, 0x09, 0x4D, 0x24
	// 0x04, 0x52, 0x09, 0x4E, 0x64
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,


	// Set MAP_EN_L_2 for map 2
	0x04, 0x52, 0x09, 0x8B, 0x07,
	// Set MAP_DPHY_DEST TO CTRL 1
	0x04, 0x52, 0x09, 0xAD, 0x15,
	// Set MAP_SRC AND DEST for data and FE/FS; [7:6]=VC, [5:0]=DT,,
	// 0x04, 0x52, 0x09, 0x8D, 0x24
	// 0x04, 0x52, 0x09, 0x8E, 0xA4
	0x04, 0x52, 0x09, 0x8D, 0x2C,
	0x04, 0x52, 0x09, 0x8E, 0xAC,
	0x04, 0x52, 0x09, 0x8F, 0x00,
	0x04, 0x52, 0x09, 0x90, 0x80,
	0x04, 0x52, 0x09, 0x91, 0x01,
	0x04, 0x52, 0x09, 0x92, 0x81,


	// Set MAP_EN_L_3 for map 3
	0x04, 0x52, 0x09, 0xCB, 0x07,
	// Set MAP_DPHY_DEST TO CTRL 1
	0x04, 0x52, 0x09, 0xED, 0x15,
	// Set MAP_SRC AND DEST for data and FE/FS; [7:6]=VC, [5:0]=DT,,
	// 0x04, 0x52, 0x09, 0xCD, 0xE4
	// 0x04, 0x52, 0x09, 0xCE, 0xE4
	0x04, 0x52, 0x09, 0xCD, 0x2C,
	0x04, 0x52, 0x09, 0xCE, 0xEC,
	0x04, 0x52, 0x09, 0xCF, 0x00,
	0x04, 0x52, 0x09, 0xD0, 0xC0,
	0x04, 0x52, 0x09, 0xD1, 0x01,
	0x04, 0x52, 0x09, 0xD2, 0xC1,

	// Enable CSI clock w/ MIPI PHY 2x4 configuration,,
	0x04, 0x52, 0x08, 0xA0, 0x04,	/* note: disabled in init */
	// Turn off unused PHYs
	0x04, 0x52, 0x08, 0xA2, 0x34,

	// End of Setup Script - MUST ONE-SHOT RESET!!!!
	// One shot reset for PHY A - HS86,,
	0x04, 0x52, 0x00, 0x18, 0x0F,
};

static uint8_t max96712_max9295_init_setting[] = {
	0x04, 0x52, 0x00, 0x13, 0x75,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x52, 0x15, 0x49, 0x75,
	0x04, 0x52, 0x16, 0x49, 0x75,
	0x04, 0x52, 0x17, 0x49, 0x75,

	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
	0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x18, 0x0F,     // data path reset
	0x00, 0xFF,
	0x00, 0xFF,

	0x04, 0x52, 0x00, 0x06, 0xF1,   // Enable 1 Links in GMSL2 mode
	0x00, 0xFF,

	// MAX9295 - Serializer config
	0x04, 0x80, 0x02, 0xbe, 0x00,   // GPIO0 output value 0
	0x04, 0x80, 0x03, 0x11, 0x40, 	// start z from B,20
	0x04, 0x80, 0x03, 0x08, 0x64, 	// z selected B,62
	0x04, 0x80, 0x00, 0x02, 0x43, 	// Video transmit z enable
	0x04, 0x80, 0x03, 0x18, 0x6c, 	// z dt1: 0x2c
	//0x04, 0x80, 0x02, 0xd6, 0x90,
	0x04, 0x80, 0x02, 0xbe, 0x18,
	0x04, 0x80, 0x02, 0xbf, 0x60,

	0x04, 0x80, 0x00, 0x44, 0x20,   // map sensor addr to 0x10.
	0x04, 0x80, 0x00, 0x45, 0x6C,

	// MAX96712 - Deserializer config
	0x04, 0x52, 0x00, 0xF0, 0x62,  	// pipe0: A-Z, pipie1: B-Z.
	0x04, 0x52, 0x00, 0xF4, 0x01,    // Enable Pipe 0

	0x04, 0x52, 0x09, 0x0B, 0x07,    // Map source 0~2 for Link A
	0x04, 0x52, 0x09, 0x2D, 0x15,    // Map source to controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,    // src vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0E, 0x2C,    // dst vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,    // src frame start
	0x04, 0x52, 0x09, 0x10, 0x00,    // dst frame start
	0x04, 0x52, 0x09, 0x11, 0x01,    // src frame end
	0x04, 0x52, 0x09, 0x12, 0x01,    // dst frame end

	0x04, 0x52, 0x08, 0xA0, 0x04,    // 2x4 mode

	0x04, 0x52, 0x08, 0xA3, 0xE4,    // Map data lanes for PHY 1
	0x04, 0x52, 0x08, 0xA4, 0xE4,    // Map data lanes for PHY 0

	0x04, 0x52, 0x09, 0x0A, 0xC0,    // 4 lanes
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,

	0x04, 0x52, 0x08, 0xA2, 0x34,    // Enable MIPI PHY0~1

// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,

// Set Data rate to be 2000Mbps/lane
	0x04, 0x52, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x34,
	0x04, 0x52, 0x04, 0x1E, 0x34,

// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
};

static uint8_t max96712_max9295_quad_init_setting_4lane[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x52, 0x15, 0x49, 0x75,
	0x04, 0x52, 0x16, 0x49, 0x75,
	0x04, 0x52, 0x17, 0x49, 0x75,

	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
	0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x18, 0x0F,     // data path reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF4,    // Link C
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x86,
	0x04, 0x86, 0x00, 0x42, 0xC4,
	0x04, 0x86, 0x00, 0x43, 0x86,
	0x04, 0x86, 0x00, 0x44, 0x26,
	0x04, 0x86, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF8,    // Link D
	0x00, 0xFF,
	0x04, 0x80, 0x00, 0x00, 0x88,
	0x04, 0x88, 0x00, 0x42, 0xC4,
	0x04, 0x88, 0x00, 0x43, 0x88,
	0x04, 0x88, 0x00, 0x44, 0x28,
	0x04, 0x88, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xFF,   // Enable all 4 Links in GMSL2 mode
	0x00, 0xFF,

	0x04, 0x82, 0x02, 0xbe, 0x00,
	0x04, 0x82, 0x03, 0x30, 0x00,   // Sensor 0 set pipe Z
	0x04, 0x82, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x82, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x82, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x82, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x82, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	// 0x04, 0x82, 0x02, 0xd6, 0x09,
	0x04, 0x82, 0x02, 0xbe, 0x18,
	0x04, 0x82, 0x02, 0xbf, 0x60,

	0x04, 0x84, 0x02, 0xbe, 0x00,
	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe X
	0x04, 0x84, 0x03, 0x31, 0x33,
	0x04, 0x84, 0x03, 0x08, 0x61,
	0x04, 0x84, 0x03, 0x11, 0x30,
	0x04, 0x84, 0x00, 0x02, 0x33,
	0x04, 0x84, 0x03, 0x14, 0x6C,
	// 0x04, 0x84, 0x02, 0xd6, 0x09,
	0x04, 0x84, 0x02, 0xbe, 0x18,
	0x04, 0x84, 0x02, 0xbf, 0x60,

	0x04, 0x86, 0x02, 0xbe, 0x00,
	0x04, 0x86, 0x03, 0x30, 0x00,   // Sensor 2 set pipe X
	0x04, 0x86, 0x03, 0x31, 0x33,
	0x04, 0x86, 0x03, 0x08, 0x61,
	0x04, 0x86, 0x03, 0x11, 0x30,
	0x04, 0x86, 0x00, 0x02, 0x33,
	0x04, 0x86, 0x03, 0x14, 0x6C,
	// 0x04, 0x86, 0x02, 0xd6, 0x09,
	0x04, 0x86, 0x02, 0xbe, 0x18,
	0x04, 0x86, 0x02, 0xbf, 0x60,

	0x04, 0x88, 0x02, 0xbe, 0x00,
	0x04, 0x88, 0x03, 0x30, 0x00,   // Sensor 3 set pipe X
	0x04, 0x88, 0x03, 0x31, 0x33,
	0x04, 0x88, 0x03, 0x08, 0x61,
	0x04, 0x88, 0x03, 0x11, 0x30,
	0x04, 0x88, 0x00, 0x02, 0x33,
	0x04, 0x88, 0x03, 0x14, 0x6C,
	// 0x04, 0x88, 0x02, 0xd6, 0x09,
	0x04, 0x88, 0x02, 0xbe, 0x18,
	0x04, 0x88, 0x02, 0xbf, 0x60,

// pipe X in link B to video pipe 1, pipe Z in link A to video pipe 0
	0x04, 0x52, 0x00, 0xF0, 0x42,
// pipe X in link D to video pipe 3, pipe X in link C to video pipe 2
	0x04, 0x52, 0x00, 0xF1, 0xC8,

	0x04, 0x52, 0x00, 0xF4, 0x0F,    // Enable Pipe 0~3

	0x04, 0x52, 0x09, 0x0B, 0x07,    // Map source 0~2 for Link A
	0x04, 0x52, 0x09, 0x2D, 0x15,    // Map source to controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,    // src vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0E, 0x2C,    // dst vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,    // src frame start
	0x04, 0x52, 0x09, 0x10, 0x00,    // dst frame start
	0x04, 0x52, 0x09, 0x11, 0x01,    // src frame end
	0x04, 0x52, 0x09, 0x12, 0x01,    // dst frame end

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x15,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	0x04, 0x52, 0x09, 0x8B, 0x07,    // Map source 0~2 for Link C
	0x04, 0x52, 0x09, 0xAD, 0x15,
	0x04, 0x52, 0x09, 0x8D, 0x2C,
	0x04, 0x52, 0x09, 0x8E, 0xAC,    // vc = 2
	0x04, 0x52, 0x09, 0x8F, 0x00,
	0x04, 0x52, 0x09, 0x90, 0x80,
	0x04, 0x52, 0x09, 0x91, 0x01,
	0x04, 0x52, 0x09, 0x92, 0x81,

	0x04, 0x52, 0x09, 0xCB, 0x07,    // Map source 0~2 for Link D
	0x04, 0x52, 0x09, 0xED, 0x15,
	0x04, 0x52, 0x09, 0xCD, 0x2C,
	0x04, 0x52, 0x09, 0xCE, 0xEC,    // vc = 3
	0x04, 0x52, 0x09, 0xCF, 0x00,
	0x04, 0x52, 0x09, 0xD0, 0xC0,
	0x04, 0x52, 0x09, 0xD1, 0x01,
	0x04, 0x52, 0x09, 0xD2, 0xC1,

	0x04, 0x52, 0x08, 0xA0, 0x04,    // 2x4 mode

	0x04, 0x52, 0x08, 0xA3, 0xE4,    // Map data lanes for PHY 1
	0x04, 0x52, 0x08, 0xA4, 0xE4,    // Map data lanes for PHY 0

	0x04, 0x52, 0x09, 0x0A, 0xC0,    // 4 lanes
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,

	0x04, 0x52, 0x08, 0xA2, 0x34,    // Enable MIPI PHY0~1

// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,

// Set Data rate to be 2000Mbps/lane
	0x04, 0x52, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x34,
	0x04, 0x52, 0x04, 0x1E, 0x34,

// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
};

static uint8_t max96712_max9295_dual_init_setting_4lane[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x52, 0x15, 0x49, 0x75,

	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
	0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x18, 0x0F,     // data path reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF3,   // Enable 2 Links in GMSL2 mode
	0x00, 0xFF,

	0x04, 0x82, 0x02, 0xbe, 0x00,
	0x04, 0x82, 0x03, 0x30, 0x00,   // Sensor 0 set pipe Z
	0x04, 0x82, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x82, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x82, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x82, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x82, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	// 0x04, 0x82, 0x02, 0xd6, 0x90,
	0x04, 0x82, 0x02, 0xbe, 0x18,
	0x04, 0x82, 0x02, 0xbf, 0x60,

	0x04, 0x84, 0x02, 0xbe, 0x00,
	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe X
	0x04, 0x84, 0x03, 0x31, 0x33,
	0x04, 0x84, 0x03, 0x08, 0x61,
	0x04, 0x84, 0x03, 0x11, 0x30,
	0x04, 0x84, 0x00, 0x02, 0x33,
	0x04, 0x84, 0x03, 0x14, 0x6C,
	// 0x04, 0x84, 0x02, 0xd6, 0x90,
	0x04, 0x84, 0x02, 0xbe, 0x18,
	0x04, 0x84, 0x02, 0xbf, 0x60,

// pipe X in link B to video pipe 1, pipe Z in link A to video pipe 0
	0x04, 0x52, 0x00, 0xF0, 0x42,

	0x04, 0x52, 0x00, 0xF4, 0x03,    // Enable Pipe 0~1

	0x04, 0x52, 0x09, 0x0B, 0x07,    // Map source 0~2 for Link A
	0x04, 0x52, 0x09, 0x2D, 0x15,    // Map source to controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,    // src vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0E, 0x2C,    // dst vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,    // src frame start
	0x04, 0x52, 0x09, 0x10, 0x00,    // dst frame start
	0x04, 0x52, 0x09, 0x11, 0x01,    // src frame end
	0x04, 0x52, 0x09, 0x12, 0x01,    // dst frame end

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x15,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	0x04, 0x52, 0x08, 0xA0, 0x04,    // 2x4 mode

	0x04, 0x52, 0x08, 0xA3, 0xE4,    // Map data lanes for PHY 1
	0x04, 0x52, 0x08, 0xA4, 0xE4,    // Map data lanes for PHY 0

	0x04, 0x52, 0x09, 0x0A, 0xC0,    // 4 lanes
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,

	0x04, 0x52, 0x08, 0xA2, 0x34,    // Enable MIPI PHY0~1

// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,

// Set Data rate to be 2000Mbps/lane
	0x04, 0x52, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x34,
	0x04, 0x52, 0x04, 0x1E, 0x34,

// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
};

static uint8_t max96712_max9295_trip_init_setting_4lane[] = {
	0x04, 0x52, 0x00, 0x13, 0x40,     // chip reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x52, 0x15, 0x49, 0x75,
	0x04, 0x52, 0x16, 0x49, 0x75,
	0x04, 0x52, 0x17, 0x49, 0x75,

	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
	0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x18, 0x0F,     // data path reset
	0x00, 0xFF,
	0x00, 0xFF,
	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF4,    // Link C
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x86,
	0x04, 0x86, 0x00, 0x42, 0xC4,
	0x04, 0x86, 0x00, 0x43, 0x86,
	0x04, 0x86, 0x00, 0x44, 0x26,
	0x04, 0x86, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF7,   // Enable 3 Links in GMSL2 mode
	0x00, 0xFF,

	0x04, 0x82, 0x02, 0xbe, 0x00,
	0x04, 0x82, 0x03, 0x30, 0x00,   // Sensor 0 set pipe Z
	0x04, 0x82, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x82, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x82, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x82, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x82, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	// 0x04, 0x82, 0x02, 0xd6, 0x90,
	0x04, 0x82, 0x02, 0xbe, 0x18,
	0x04, 0x82, 0x02, 0xbf, 0x60,

	0x04, 0x84, 0x02, 0xbe, 0x00,
	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe X
	0x04, 0x84, 0x03, 0x31, 0x33,
	0x04, 0x84, 0x03, 0x08, 0x61,
	0x04, 0x84, 0x03, 0x11, 0x30,
	0x04, 0x84, 0x00, 0x02, 0x33,
	0x04, 0x84, 0x03, 0x14, 0x6C,
	// 0x04, 0x84, 0x02, 0xd6, 0x90,
	0x04, 0x84, 0x02, 0xbe, 0x18,
	0x04, 0x84, 0x02, 0xbf, 0x60,

	0x04, 0x86, 0x02, 0xbe, 0x00,
	0x04, 0x86, 0x03, 0x30, 0x00,   // Sensor 2 set pipe X
	0x04, 0x86, 0x03, 0x31, 0x33,
	0x04, 0x86, 0x03, 0x08, 0x61,
	0x04, 0x86, 0x03, 0x11, 0x30,
	0x04, 0x86, 0x00, 0x02, 0x33,
	0x04, 0x86, 0x03, 0x14, 0x6C,
	// 0x04, 0x86, 0x02, 0xd6, 0x90,
	0x04, 0x86, 0x02, 0xbe, 0x18,
	0x04, 0x86, 0x02, 0xbf, 0x60,

// pipe X in link B to video pipe 1, pipe Z in link A to video pipe 0
	0x04, 0x52, 0x00, 0xF0, 0x42,
// pipe X in link D to video pipe 3, pipe X in link C to video pipe 2
	0x04, 0x52, 0x00, 0xF1, 0xC8,

	0x04, 0x52, 0x00, 0xF4, 0x07,    // Enable Pipe 0~2

	0x04, 0x52, 0x09, 0x0B, 0x07,    // Map source 0~2 for Link A
	0x04, 0x52, 0x09, 0x2D, 0x15,    // Map source to controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,    // src vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0E, 0x2C,    // dst vc && datatype, vc = 0, RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,    // src frame start
	0x04, 0x52, 0x09, 0x10, 0x00,    // dst frame start
	0x04, 0x52, 0x09, 0x11, 0x01,    // src frame end
	0x04, 0x52, 0x09, 0x12, 0x01,    // dst frame end

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x15,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	0x04, 0x52, 0x09, 0x8B, 0x07,    // Map source 0~2 for Link C
	0x04, 0x52, 0x09, 0xAD, 0x15,
	0x04, 0x52, 0x09, 0x8D, 0x2C,
	0x04, 0x52, 0x09, 0x8E, 0xAC,    // vc = 2
	0x04, 0x52, 0x09, 0x8F, 0x00,
	0x04, 0x52, 0x09, 0x90, 0x80,
	0x04, 0x52, 0x09, 0x91, 0x01,
	0x04, 0x52, 0x09, 0x92, 0x81,

	0x04, 0x52, 0x08, 0xA0, 0x04,    // 2x4 mode

	0x04, 0x52, 0x08, 0xA3, 0xE4,    // Map data lanes for PHY 1
	0x04, 0x52, 0x08, 0xA4, 0xE4,    // Map data lanes for PHY 0

	0x04, 0x52, 0x09, 0x0A, 0xC0,    // 4 lanes
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,

	0x04, 0x52, 0x08, 0xA2, 0x34,    // Enable MIPI PHY0~1

// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,

// Set Data rate to be 2000Mbps/lane
	0x04, 0x52, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x34,
	0x04, 0x52, 0x04, 0x1E, 0x34,

// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
};

/* weisen0820 + sensingx3c -> max96712: A+B */
uint8_t weisen_max96712_max9295_dual_init_setting[] = {
	// reset 0820
	0x04, 0x52, 0x00, 0x13, 0x40, 	// reset all.
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x52, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x52, 0x15, 0x49, 0x75,

	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
	0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x18, 0x0F, 	// One-shot link reset for all
	0x00, 0xff,
	0x00, 0xff,

	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x32,
	0x04, 0x82, 0x00, 0x45, 0x30,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF3,   // Enable 2 Links in GMSL2 mode
	0x00, 0xFF,

	// LinkA: MAX9295 - Serializer config
	0x04, 0x82, 0x00, 0x10, 0x15,
	0x04, 0x82, 0x00, 0x12, 0x14,
	0x04, 0x82, 0x03, 0x11, 0x40,	 // start x/y/z/u from B,40
	0x04, 0x82, 0x03, 0x08, 0x64,	 // x/y/z/u selected B,64
	0x04, 0x82, 0x00, 0x02, 0x43,	 // Video transmit enable  //transmit Z,43

	0x04, 0x82, 0x03, 0x18, 0x6c,

	0x04, 0x82, 0x02, 0xD6, 0x80,
	0x00, 0x20,
	0x04, 0x82, 0x02, 0xD6, 0x9C,
	0x00, 0x20,
	0x04, 0x82, 0x00, 0x58, 0x80,

	// LinkB: MAX9295 - Serializer config
	0x04, 0x84, 0x00, 0x10, 0x15,
	0x04, 0x84, 0x00, 0x12, 0x14,
	0x04, 0x84, 0x03, 0x11, 0x40,	 // start x/y/z/u from B,40
	0x04, 0x84, 0x03, 0x08, 0x64,	 // x/y/z/u selected B,64
	0x04, 0x84, 0x00, 0x02, 0x43,	 // Video transmit enable  //transmit Z,43

	0x04, 0x84, 0x03, 0x18, 0x6c,

	0x04, 0x84, 0x02, 0xbe, 0x18,
	0x04, 0x84, 0x02, 0xbf, 0x60,
	0x04, 0x84, 0x00, 0x58, 0x80,

	// MAX96712 - Deserializer config
	// Video Pipe Selection
	0x04, 0x52, 0x00, 0xF0, 0x62,  	// pipe0: A-Z, pipie1: B-Z.
	// 0x04, 0x52, 0x00, 0xF1, 0xEA,  	// pipe2: C-Z, pipie3: D-Z.
	// 0x04, 0x52, 0x00, 0xF2, 0x40, 	// pipe4: A-X, pipie5: B-X.
	// 0x04, 0x52, 0x00, 0xF3, 0xC8, 	// pipe6: D-X, pipie7: D-X.
	0x04, 0x52, 0x00, 0xF4, 0x03,  	// Turn on pipe 0+1.
	0x04, 0x52, 0x00, 0x60, 0x44,  	// a/b-z: rx crc.

	// Video Pipe to MIPI Controller Mapping
	// RAW12, video pipe 0
	0x04, 0x52, 0x09, 0x0B, 0x07,  	// pipe0: s/d 0~2 enable.
	0x04, 0x52, 0x09, 0x2D, 0x15,  	// pipe0: s/d 0~2 map to MIPI Controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,
	0x04, 0x52, 0x09, 0x0E, 0x2C,  	// pipe0: s/d 0 map data to VC0:RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,
	0x04, 0x52, 0x09, 0x10, 0x00,  	// pipe0: s/d 1 map FS to VC0
	0x04, 0x52, 0x09, 0x11, 0x01,
	0x04, 0x52, 0x09, 0x12, 0x01,  	// pipe0: s/d 2 map FS to VC0

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x15,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	// MIPI PHY Setting
	// Set Des in 2x4 mode
	0x04, 0x52, 0x08, 0xA0, 0x04,
	// Set Lane Mapping for 4-lane port A
	0x04, 0x52, 0x08, 0xA3, 0xE4,
	0x04, 0x52, 0x08, 0xA4, 0xE4,
	// Set 4 lane D-PHY
	0x04, 0x52, 0x09, 0x0A, 0xC0,
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,
	// Turn on MIPI PHYs 0+1
	0x04, 0x52, 0x08, 0xA2, 0x34,

	// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,
	// Set Data rate to be 2500Mbps/lane
	// 0x04, 0x52, 0x04, 0x15, 0x39,
	0x04, 0x52, 0x04, 0x18, 0x39,
	// 0x04, 0x52, 0x04, 0x1B, 0x39,
	// 0x04, 0x52, 0x04, 0x1E, 0x39,
	// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
	0x04, 0x52, 0x04, 0x0B, 0x62,  	// stream on
};

/* sensing0820 + sensingx3c -> max96712: A+B */
uint8_t sensing_max96712_max9295_dual_init_setting[] = {
	// reset 0820
	0x04, 0x52, 0x00, 0x13, 0x40, 	// reset all.
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x52, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x52, 0x15, 0x49, 0x75,

	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
	0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x18, 0x0F, 	// One-shot link reset for all
	0x00, 0xff,
	0x00, 0xff,

	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x20,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF3,   // Enable 2 Links in GMSL2 mode
	0x00, 0xFF,

	// LinkA: MAX9295 - Serializer config
	0x04, 0x82, 0x03, 0x11, 0x40, 	// start z from B,20
	0x04, 0x82, 0x03, 0x08, 0x64, 	// z selected B,62
	0x04, 0x82, 0x00, 0x02, 0x43, 	// Video transmit z enable
	0x04, 0x82, 0x03, 0x18, 0x6c, 	// z dt1: 0x2c

	0x04, 0x82, 0x03, 0xf0, 0x51,
	0x04, 0x82, 0x00, 0x03, 0x03,
	0x04, 0x82, 0x00, 0x06, 0xb1,
	0x04, 0x82, 0x02, 0xbe, 0x18,
	0x04, 0x82, 0x02, 0xbf, 0x60,
	0x04, 0x82, 0x00, 0x58, 0x80,	// z: tx crc.

	// LinkB: MAX9295 - Serializer config
	0x04, 0x84, 0x03, 0x11, 0x40, 	// start z from B,20
	0x04, 0x84, 0x03, 0x08, 0x64, 	// z selected B,62
	0x04, 0x84, 0x00, 0x02, 0x43, 	// Video transmit z enable
	0x04, 0x84, 0x03, 0x18, 0x6c, 	// z dt1: 0x2c

	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x00, 0x03, 0x03,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xbe, 0x18,
	0x04, 0x84, 0x02, 0xbf, 0x60,
	0x04, 0x84, 0x00, 0x58, 0x80,	// z: tx crc.

	// MAX96712 - Deserializer config
	// Video Pipe Selection
	0x04, 0x52, 0x00, 0xF0, 0x62,  	// pipe0: A-Z, pipie1: B-Z.
	// 0x04, 0x52, 0x00, 0xF1, 0xEA,  	// pipe2: C-Z, pipie3: D-Z.
	// 0x04, 0x52, 0x00, 0xF2, 0x40, 	// pipe4: A-X, pipie5: B-X.
	// 0x04, 0x52, 0x00, 0xF3, 0xC8, 	// pipe6: D-X, pipie7: D-X.
	0x04, 0x52, 0x00, 0xF4, 0x03,  	// Turn on pipe 0+1.
	0x04, 0x52, 0x00, 0x60, 0x44,  	// a/b-z: rx crc.

	// Video Pipe to MIPI Controller Mapping
	// RAW12, video pipe 0
	0x04, 0x52, 0x09, 0x0B, 0x07,  	// pipe0: s/d 0~2 enable.
	0x04, 0x52, 0x09, 0x2D, 0x15,  	// pipe0: s/d 0~2 map to MIPI Controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,
	0x04, 0x52, 0x09, 0x0E, 0x2C,  	// pipe0: s/d 0 map data to VC0:RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,
	0x04, 0x52, 0x09, 0x10, 0x00,  	// pipe0: s/d 1 map FS to VC0
	0x04, 0x52, 0x09, 0x11, 0x01,
	0x04, 0x52, 0x09, 0x12, 0x01,  	// pipe0: s/d 2 map FS to VC0

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x15,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	// MIPI PHY Setting
	// Set Des in 2x4 mode
	0x04, 0x52, 0x08, 0xA0, 0x04,
	// Set Lane Mapping for 4-lane port A
	0x04, 0x52, 0x08, 0xA3, 0xE4,
	0x04, 0x52, 0x08, 0xA4, 0xE4,
	// Set 4 lane D-PHY
	0x04, 0x52, 0x09, 0x0A, 0xC0,
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,
	// Turn on MIPI PHYs 0+1
	0x04, 0x52, 0x08, 0xA2, 0x34,

	// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,
	// Set Data rate to be 2500Mbps/lane
	// 0x04, 0x52, 0x04, 0x15, 0x39,
	0x04, 0x52, 0x04, 0x18, 0x39,
	// 0x04, 0x52, 0x04, 0x1B, 0x39,
	// 0x04, 0x52, 0x04, 0x1E, 0x39,
	// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
	0x04, 0x52, 0x04, 0x0B, 0x62,  	// stream on
};

/* weisen0820 + galaxyx3c -> max96712: A+B */
uint8_t weisen_max96712_max9295_max96717_init_setting[] = {
	// reset 0820
	0x04, 0x52, 0x00, 0x13, 0x40, 	// reset all.
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x52, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x52, 0x15, 0x49, 0x75,

	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
	0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x10, 0x12,   // Link A:6Gbps B:3Gbps
	0x04, 0x52, 0x00, 0x18, 0x0F, 	// One-shot link reset for all
	0x00, 0xff,
	0x00, 0xff,

	0x04, 0x52, 0x00, 0x06, 0xF1,     // Link A
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x32,
	0x04, 0x82, 0x00, 0x45, 0x30,

	0x04, 0x52, 0x00, 0x06, 0xF2,     // Link B
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xF3,   // Enable 2 Links in GMSL2 mode
	0x00, 0xFF,

	// LinkA: MAX9295 - Serializer config
	0x04, 0x82, 0x00, 0x10, 0x15,
	0x04, 0x82, 0x00, 0x12, 0x14,
	0x04, 0x82, 0x03, 0x11, 0x40,	 // start x/y/z/u from B,40
	0x04, 0x82, 0x03, 0x08, 0x64,	 // x/y/z/u selected B,64
	0x04, 0x82, 0x00, 0x02, 0x43,	 // Video transmit enable  //transmit Z,43

	0x04, 0x82, 0x03, 0x18, 0x6c,

	0x04, 0x82, 0x02, 0xD6, 0x80,
	0x00, 0x20,
	0x04, 0x82, 0x02, 0xD6, 0x9C,
	0x00, 0x20,
	0x04, 0x82, 0x00, 0x58, 0x80,

	// LinkB: MAX96717 - Serializer config
	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xbf, 0x60,

	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe Z
	0x04, 0x84, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x84, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x84, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x84, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x84, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x84, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x84, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x05, 0x70, 0x1c,
	0x04, 0x84, 0x05, 0x70, 0x0c,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xd3, 0x90,
	0x04, 0x84, 0x00, 0x58, 0x80, 	// z: tx crc.

	// MAX96712 - Deserializer config
	// Video Pipe Selection
	0x04, 0x52, 0x00, 0xF0, 0x62,  	// pipe0: A-Z, pipie1: B-Z.
	// 0x04, 0x52, 0x00, 0xF1, 0xEA,  	// pipe2: C-Z, pipie3: D-Z.
	// 0x04, 0x52, 0x00, 0xF2, 0x40, 	// pipe4: A-X, pipie5: B-X.
	// 0x04, 0x52, 0x00, 0xF3, 0xC8, 	// pipe6: D-X, pipie7: D-X.
	0x04, 0x52, 0x00, 0xF4, 0x03,  	// Turn on pipe 0+1.
	0x04, 0x52, 0x00, 0x60, 0x44,  	// a/b-z: rx crc.

	// Video Pipe to MIPI Controller Mapping
	// RAW12, video pipe 0
	0x04, 0x52, 0x09, 0x0B, 0x07,  	// pipe0: s/d 0~2 enable.
	0x04, 0x52, 0x09, 0x2D, 0x15,  	// pipe0: s/d 0~2 map to MIPI Controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,
	0x04, 0x52, 0x09, 0x0E, 0x2C,  	// pipe0: s/d 0 map data to VC0:RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,
	0x04, 0x52, 0x09, 0x10, 0x00,  	// pipe0: s/d 1 map FS to VC0
	0x04, 0x52, 0x09, 0x11, 0x01,
	0x04, 0x52, 0x09, 0x12, 0x01,  	// pipe0: s/d 2 map FS to VC0

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 for Link B
	0x04, 0x52, 0x09, 0x6D, 0x15,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	// MIPI PHY Setting
	// Set Des in 2x4 mode
	0x04, 0x52, 0x08, 0xA0, 0x04,
	// Set Lane Mapping for 4-lane port A
	0x04, 0x52, 0x08, 0xA3, 0xE4,
	0x04, 0x52, 0x08, 0xA4, 0xE4,
	// Set 4 lane D-PHY
	0x04, 0x52, 0x09, 0x0A, 0xC0,
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,
	// Turn on MIPI PHYs 0+1
	0x04, 0x52, 0x08, 0xA2, 0x34,

	// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,
	// Set Data rate to be 2500Mbps/lane
	// 0x04, 0x52, 0x04, 0x15, 0x39,
	0x04, 0x52, 0x04, 0x18, 0x39,
	// 0x04, 0x52, 0x04, 0x1B, 0x39,
	// 0x04, 0x52, 0x04, 0x1E, 0x39,
	// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
	0x04, 0x52, 0x04, 0x0B, 0x62,  	// stream on
};

/* weisen0820 + galaxyx3c -> max96712: D+C -> CSI A */
uint8_t galaxy_with_max96712_max9295_max96717_init_setting[] = {
	// reset 0820
	0x04, 0x52, 0x00, 0x13, 0x40, 	// reset all.
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x52, 0x16, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x52, 0x17, 0x49, 0x75,
	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
    0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x11, 0x21,   // Link D:6Gbps C:3Gbps
	0x04, 0x52, 0x00, 0x18, 0x0F, 	// One-shot link reset for all
	0x00, 0xff,
	0x00, 0xff,

	0x04, 0x52, 0x00, 0x06, 0xF8,     // Link D
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x20,

	0x04, 0x52, 0x00, 0x06, 0xF4,     // Link C
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xFC,   // Enable 2 Links in GMSL2 mode
	0x00, 0xFF,

	// LinkD: MAX9295 - Serializer config
	0x04, 0x82, 0x00, 0x10, 0x15,
	0x04, 0x82, 0x00, 0x12, 0x14,
	0x04, 0x82, 0x03, 0x11, 0x40,	 // start x/y/z/u from B,40
	0x04, 0x82, 0x03, 0x08, 0x64,	 // x/y/z/u selected B,64
	0x04, 0x82, 0x00, 0x02, 0x43,	 // Video transmit enable  //transmit Z,43

	0x04, 0x82, 0x03, 0x18, 0x6c,

	0x04, 0x82, 0x02, 0xD6, 0x80,
	0x00, 0x20,
	0x04, 0x82, 0x02, 0xD6, 0x9C,
	0x00, 0x20,
	0x04, 0x82, 0x00, 0x58, 0x80,

	// LinkC: MAX96717 - Serializer config
	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xbf, 0x60,

	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe Z
	0x04, 0x84, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x84, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x84, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x84, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x84, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x84, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x84, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x05, 0x70, 0x1c,
	0x04, 0x84, 0x05, 0x70, 0x0c,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xd3, 0x90,
	0x04, 0x84, 0x00, 0x58, 0x80, 	// z: tx crc.

	// MAX96712 - Deserializer config
	// Video Pipe Selection
	0x04, 0x52, 0x00, 0xF0, 0xAE,  	// pipe0: D-Z, pipie1: C-Z.
	// 0x04, 0x52, 0x00, 0xF1, 0xEA,  	// pipe2: C-Z, pipie3: D-Z.
	// 0x04, 0x52, 0x00, 0xF2, 0x40, 	// pipe4: A-X, pipie5: B-X.
	// 0x04, 0x52, 0x00, 0xF3, 0xC8, 	// pipe6: D-X, pipie7: D-X.
	0x04, 0x52, 0x00, 0xF4, 0x03,  	// Turn on pipe 0+1.
	0x04, 0x52, 0x00, 0x60, 0x44,  	// a/b-z: rx crc.

	// Video Pipe to MIPI Controller Mapping
	// RAW12, video pipe 0
	0x04, 0x52, 0x09, 0x0B, 0x07,  	// pipe0: s/d 0~2 pipe0: CSI-A:VC0.
	0x04, 0x52, 0x09, 0x2D, 0x15,  	// pipe0: s/d 0~2 map to MIPI Controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,
	0x04, 0x52, 0x09, 0x0E, 0x2C,  	// pipe0: s/d 0 map data to VC0:RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,
	0x04, 0x52, 0x09, 0x10, 0x00,  	// pipe0: s/d 1 map FS to VC0
	0x04, 0x52, 0x09, 0x11, 0x01,
	0x04, 0x52, 0x09, 0x12, 0x01,  	// pipe0: s/d 2 map FS to VC0

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 pipi1: CSI-A: VC1.
	0x04, 0x52, 0x09, 0x6D, 0x15,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	// MIPI PHY Setting
	// Set Des in 2x4 mode
	0x04, 0x52, 0x08, 0xA0, 0x04,
	// Set Lane Mapping for 4-lane port A
	0x04, 0x52, 0x08, 0xA3, 0xE4,
	0x04, 0x52, 0x08, 0xA4, 0xE4,
	// Set 4 lane D-PHY
	0x04, 0x52, 0x09, 0x0A, 0xC0,
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,
	// Turn on MIPI PHYs 0+1
	0x04, 0x52, 0x08, 0xA2, 0x34,

	// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,
	// Set Data rate to be 2000Mbps/lane
	// 0x04, 0x52, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x34,
	// 0x04, 0x52, 0x04, 0x1E, 0x34,
	// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
	0x04, 0x52, 0x04, 0x0B, 0x62,  	// stream on
};

/* weisen0820 + galaxyx3c -> max96712: D+C -> CSI A+B */
uint8_t galaxy_sepa_max96712_max9295_max96717_init_setting[] = {
	// reset 0820
	0x04, 0x52, 0x00, 0x13, 0x40, 	// reset all.
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x52, 0x16, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x52, 0x17, 0x49, 0x75,
	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
    0x04, 0x52, 0x06, 0xC2, 0x10,

	0x04, 0x52, 0x00, 0x11, 0x21,   // Link D:6Gbps C:3Gbps
	0x04, 0x52, 0x00, 0x18, 0x0F, 	// One-shot link reset for all
	0x00, 0xff,
	0x00, 0xff,

	0x04, 0x52, 0x00, 0x06, 0xF8,     // Link D
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x20,

	0x04, 0x52, 0x00, 0x06, 0xF4,     // Link C
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xFC,   // Enable 2 Links in GMSL2 mode
	0x00, 0xFF,

	// LinkD: MAX9295 - Serializer config
	0x04, 0x82, 0x00, 0x10, 0x15,
	0x04, 0x82, 0x00, 0x12, 0x14,
	0x04, 0x82, 0x03, 0x11, 0x40,	 // start x/y/z/u from B,40
	0x04, 0x82, 0x03, 0x08, 0x64,	 // x/y/z/u selected B,64
	0x04, 0x82, 0x00, 0x02, 0x43,	 // Video transmit enable  //transmit Z,43

	0x04, 0x82, 0x03, 0x18, 0x6c,

	0x04, 0x82, 0x02, 0xD6, 0x80,
	0x00, 0x20,
	0x04, 0x82, 0x02, 0xD6, 0x9C,
	0x00, 0x20,
	0x04, 0x82, 0x00, 0x58, 0x80,

	// LinkC: MAX96717 - Serializer config
	0x04, 0x84, 0x02, 0xd3, 0x00,
	0x04, 0x84, 0x02, 0xbe, 0x90,
	0x04, 0x84, 0x02, 0xbf, 0x60,

	0x04, 0x84, 0x03, 0x30, 0x00,   // Sensor 1 set pipe Z
	0x04, 0x84, 0x03, 0x31, 0x33,   // 4 Lanes
	0x04, 0x84, 0x03, 0x32, 0xE0,   // Lane mapping for PHY 1
	0x04, 0x84, 0x03, 0x33, 0x04,   // Lane mapping for PHY 2
	0x04, 0x84, 0x03, 0x08, 0x64,   // Enable PORT B && pipe Z
	0x04, 0x84, 0x03, 0x11, 0x40,   // stat pipe Z for PORT B
	0x04, 0x84, 0x00, 0x02, 0x43,   // transmit enable for pipe Z
	0x04, 0x84, 0x03, 0x18, 0x6C,   // Datatype for pipe Z
	0x04, 0x84, 0x03, 0x83, 0x00,
	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x03, 0xf1, 0x09,
	0x04, 0x84, 0x05, 0x70, 0x1c,
	0x04, 0x84, 0x05, 0x70, 0x0c,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xd3, 0x90,
	0x04, 0x84, 0x00, 0x58, 0x80, 	// z: tx crc.

	// MAX96712 - Deserializer config
	// Video Pipe Selection
	0x04, 0x52, 0x00, 0xF0, 0xAE,  	// pipe0: D-Z, pipie1: C-Z.
	// 0x04, 0x52, 0x00, 0xF1, 0xEA,  	// pipe2: C-Z, pipie3: D-Z.
	// 0x04, 0x52, 0x00, 0xF2, 0x40, 	// pipe4: A-X, pipie5: B-X.
	// 0x04, 0x52, 0x00, 0xF3, 0xC8, 	// pipe6: D-X, pipie7: D-X.
	0x04, 0x52, 0x00, 0xF4, 0x03,  	// Turn on pipe 0+1.
	0x04, 0x52, 0x00, 0x60, 0x44,  	// a/b-z: rx crc.

	// Video Pipe to MIPI Controller Mapping
	// RAW12, video pipe 0
	0x04, 0x52, 0x09, 0x0B, 0x07,  	// pipe0: s/d 0~2 pipe0: CSI-A: VC0.
	0x04, 0x52, 0x09, 0x2D, 0x15,  	// pipe0: s/d 0~2 map to MIPI Controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,
	0x04, 0x52, 0x09, 0x0E, 0x2C,  	// pipe0: s/d 0 map data to VC0:RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,
	0x04, 0x52, 0x09, 0x10, 0x00,  	// pipe0: s/d 1 map FS to VC0
	0x04, 0x52, 0x09, 0x11, 0x01,
	0x04, 0x52, 0x09, 0x12, 0x01,  	// pipe0: s/d 2 map FS to VC0

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 pipe1: CSI-B: VC0.
	0x04, 0x52, 0x09, 0x6D, 0x2A,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x2C,    // vc = 0
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x00,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x01,

	// MIPI PHY Setting
	// Set Des in 2x4 mode
	0x04, 0x52, 0x08, 0xA0, 0x04,
	// Set Lane Mapping for 4-lane port A
	0x04, 0x52, 0x08, 0xA3, 0xE4,
	0x04, 0x52, 0x08, 0xA4, 0xE4,
	// Set 4 lane D-PHY
	0x04, 0x52, 0x09, 0x0A, 0xC0,
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,
	// Turn on MIPI PHYs 0~3
	0x04, 0x52, 0x08, 0xA2, 0xF4,

	// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,
	// Set Data rate to be 1200Mbps/lane
	// 0x04, 0x52, 0x04, 0x15, 0x2C,
	0x04, 0x52, 0x04, 0x18, 0x2C,
	0x04, 0x52, 0x04, 0x1B, 0x2C,
	// 0x04, 0x52, 0x04, 0x1E, 0x2C,
	// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
	0x04, 0x52, 0x04, 0x0B, 0x62,  	// stream on
};

uint8_t sunny_max96718_init_setting[] = {
#ifndef POC_RETRY_POLICY
	0x03, 0x52, 0x01, 0x00,
	0x00, 0xff,
	0x03, 0x52, 0x01, 0x1f,
	0x00, 0xff,
#endif
	0x04, 0x90, 0x00, 0x10, 0xf3,
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x90, 0x14, 0x49, 0xF5,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x90, 0x15, 0x49, 0xF5,

	0x04, 0x90, 0x00, 0x04, 0x01,		// 96717:GMSL2 3Gbps

	// MAX9296 - Deserializer config
	0x04, 0x90, 0x03, 0x13, 0x00,
	0x04, 0x90, 0x03, 0x30, 0x04,   // 2*4 PORTA(PHY0+PHY1) PORTB(PHY2+PHY3)
	0x04, 0x90, 0x03, 0x16, 0x80,   // y dt: 0x2c (x dt: 0x00)
	0x04, 0x90, 0x03, 0x17, 0xBC,   // z dt: 0x2c
	0x04, 0x90, 0x03, 0x18, 0x00,   // (u dt: 0x00)
	0x04, 0x90, 0x03, 0x19, 0x6C,   // y z dt: 12
	0x04, 0x90, 0x03, 0x1A, 0x00,
	0x04, 0x90, 0x03, 0x14, 0x10,   // y: vc1
	0x04, 0x90, 0x03, 0x15, 0x00,   // z: vc0

	// 0x04, 0x90, 0x03, 0x1D, 0xAC,	// y: soft override.
	// 0x04, 0x90, 0x03, 0x20, 0x79,	// z: soft overfide, Port A 2.5G
	// 0x04, 0x90, 0x03, 0x23, 0x39,   // PortB: 2.5G

	// y map to vc1 of PortA.
	0x04, 0x90, 0x04, 0x4B, 0x07,	 // Enable 3 Mappings
	// 0x04, 0x50, 0x04, 0x6D, 0x2a,	// Destionation Controller = Controller 1. Controller 1 sends data to MIPI Port A
	// 0x04, 0x90, 0x04, 0x6D, 0x15,
	// For the following MSB 2 bits = VC, LSB 6 bits =DT
	0x04, 0x90, 0x04, 0x4D, 0x2C,	 // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4E, 0x6C,	 // DEST 0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x4F, 0x00,	 // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x50, 0x40,	 // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x51, 0x01,	 // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x52, 0x41,	 // DEST DT = Frame End

	// z map to vc0 of PortA.
	0x04, 0x90, 0x04, 0x8B, 0x07,	 // Enable 3 Mappings
	// 0x04, 0x50, 0x04, 0xAD, 0x2a, // Destionation Controller = Controller 1. Controller 2 sends data to MIPI Port A
	// 0x04, 0x90, 0x04, 0xAD, 0x15,
	// For the following MSB 2 bits = VC, LSB 6 bits = DT
	0x04, 0x90, 0x04, 0x8D, 0x2C,	 // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x90, 0x04, 0x8E, 0x2C,	 // DEST 0b01101100, DT = 0x2C VC=1
	0x04, 0x90, 0x04, 0x8F, 0x00,	 // SRC  DT = Frame Start
	0x04, 0x90, 0x04, 0x90, 0x00,	 // DEST DT = Frame Start
	0x04, 0x90, 0x04, 0x91, 0x01,	 // SRC  DT = Frame End
	0x04, 0x90, 0x04, 0x92, 0x01,	 // DEST DT = Frame End

	0x04, 0x90, 0x03, 0x25, 0x80,
	0x04, 0x90, 0x03, 0x13, 0x02,	 // MIPI output enable
};

uint32_t max96717_setting_rclk[] = {
	// MAX96717 - RCLK config
	0x03f0, 0x5B,	 // reset reference generation PLL
	0x02d6, 0x00,	 // Mfp8 output low
	0x0570, 0x0c,	 // disable PIO to mfp4
	0x03f0, 0x59,	 // Enable reference pll, 24M
	0x0003, 0x03,	 // Route RCLK to MFP4, R PLL out
	0x0006, 0xb0,	 // RCLK output enabale
	0x02d6, 0x90,	 // Mfp8 output high sensor reset
};

uint8_t ofilm_max96718_max96717_init_setting[] = {
#ifndef POC_RETRY_POLICY
	0x03, 0x52, 0x01, 0x00,
	0x00, 0xff,
	0x03, 0x52, 0x01, 0x1f,
	0x00, 0xff,
#endif
	0x04, 0x50, 0x00, 0x10, 0xf3,
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x50, 0x14, 0x49, 0xF5,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x50, 0x15, 0x49, 0xF5,

	0x04, 0x50, 0x00, 0x01, 0x01,  // LinkA:GMSL2 3Gbps
	0x00, 0x64,

	// LINKA MAX96717 config
	0x04, 0x84, 0x00, 0x02, 0x43,	 // enable pipe Z
	0x04, 0x84, 0x03, 0x18, 0x6c,	 // date type
	0x04, 0x84, 0x03, 0xf1, 0x09,	 // Pclk out gpio4
	0x04, 0x84, 0x03, 0xf0, 0x51,	 // enable rpll
	0x04, 0x84, 0x00, 0x06, 0xb1,	 // RCLK output enable, I2c selected
	0x04, 0x84, 0x00, 0x5b, 0x01,	 // Pipe Z strame ID 0x01
	0x04, 0x84, 0x00, 0x44, 0x22,	 // map sensor addr to 0x10.
	0x04, 0x84, 0x00, 0x45, 0x6C,
	0x00, 0x20,

	// MAX96718 - Deserializer config
	0x04, 0x50, 0x03, 0x13, 0x00,
	0x04, 0x50, 0x03, 0x30, 0x04, 	 // 2*4 PORTA(PHY0+PHY1) PORTB(PHY2+PHY3)
	0x04, 0x50, 0x03, 0x16, 0x80, 	 // y dt: 0x2c (x dt: 0x00)
	0x04, 0x50, 0x03, 0x17, 0xBC, 	 // z dt: 0x2c
	0x04, 0x50, 0x03, 0x18, 0x00, 	 // (u dt: 0x00)
	0x04, 0x50, 0x03, 0x19, 0x6C, 	 // y z dt: 12
	0x04, 0x50, 0x03, 0x1A, 0x00,
	0x04, 0x50, 0x03, 0x14, 0x10, 	 // y: vc1
	0x04, 0x50, 0x03, 0x15, 0x00, 	 // z: vc0
	0x04, 0x50, 0x03, 0x1D, 0x2C, 	 // y: soft override.
	0x04, 0x50, 0x03, 0x20, 0x2C, 	 // z: soft overfide, Port A 2.5G

	0x04, 0x50, 0x03, 0x25, 0x80,	 // wait for a new frame
};

/* ovx8b + ovx3c -> max96718 */
uint8_t lce_max96718_max96717_max96717_init_setting[] = {
#ifndef POC_RETRY_POLICY
	0x03, 0x52, 0x01, 0x00,
	0x00, 0xff,
	0x03, 0x52, 0x01, 0x1f,
	0x00, 0xff,
#endif
	0x04, 0x50, 0x00, 0x10, 0xf3,
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x50, 0x14, 0x49, 0xF5,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x50, 0x15, 0x49, 0xF5,

	0x04, 0x50, 0x00, 0x01, 0x01,  // LinkA:GMSL2 3Gbps
	0x04, 0x50, 0x00, 0x10, 0x23,  // choose LINKA+LINKB and rest LINKA
	0x00, 0x32,

	// LINKA + LINKB: MAX96717 config
	0x04, 0x50, 0x00, 0x03, 0x53,
	0x00, 0x5F,

	// linkA max96717 ovx3c - Serializer config
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x02, 0x43,  // enable pipe Z
	0x04, 0x82, 0x03, 0x83, 0x00,
	0x04, 0x82, 0x03, 0x18, 0x6c,
	0x04, 0x82, 0x03, 0xf1, 0x09,
	0x04, 0x82, 0x03, 0xf0, 0x51,
	0x04, 0x82, 0x00, 0x06, 0xb1,
	0x04, 0x82, 0x00, 0x5b, 0x01,  // Pipe Z strame ID 0x01
	0x04, 0x82, 0x00, 0x44, 0x22,  // map sensor addr to 0x10.
	0x04, 0x82, 0x00, 0x45, 0x6C,
	0x04, 0x82, 0x00, 0x42, 0xA2,  // eeprom
	0x04, 0x82, 0x00, 0x43, 0xAE,
	0x00, 0x20,

	// linkA max96717 ovx8b - Serializer config
	0x04, 0x84, 0x00, 0x02, 0x43,  // enable pipe Z
	0x04, 0x84, 0x03, 0x08, 0x64,  // pipe Z selected B,62
	0x04, 0x84, 0x03, 0x11, 0x40,  // start Z from B,20
	0x04, 0x84, 0x00, 0x5b, 0x02,  // Pipe Z strame ID 0x02
	0x04, 0x84, 0x03, 0x18, 0x6c,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,
	0x04, 0x84, 0x00, 0x42, 0xA4,  // eeprom
	0x04, 0x84, 0x00, 0x43, 0xAE,

	// MAX9296 - Deserializer config
	0x04, 0x50, 0x03, 0x13, 0x00,
	0x04, 0x50, 0x03, 0x30, 0x04,  // 2*4 PORTA(PHY0+PHY1) PORTB(PHY2+PHY3)
	0x04, 0x50, 0x03, 0x16, 0x80,  // y dt: 0x2c (x dt: 0x00)
	0x04, 0x50, 0x03, 0x17, 0xBC,  // z dt: 0x2c
	0x04, 0x50, 0x03, 0x18, 0x00,  // (u dt: 0x00)
	0x04, 0x50, 0x03, 0x19, 0x6C,  // y z dt: 12
	0x04, 0x50, 0x03, 0x1A, 0x00,
	0x04, 0x50, 0x03, 0x14, 0x10,  // y: vc1
	0x04, 0x50, 0x03, 0x15, 0x00,  // z: vc0

	0x04, 0x50, 0x03, 0x1D, 0xAC,  // y: soft override.
	0x04, 0x50, 0x03, 0x20, 0x7C,  // z: soft overfide, Port A 2.5G
	// 0x04, 0x50, 0x03, 0x23, 0x39,	// PortB: 2.5G

	// y map to vc1
	0x04, 0x50, 0x04, 0x4B, 0x07,  // Enable 3 Mappings
	0x04, 0x50, 0x04, 0x4D, 0x2C,  // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x50, 0x04, 0x4E, 0x6C,  // DEST 0b00101100, DT = 0x2C VC=1
	0x04, 0x50, 0x04, 0x4F, 0x00,  // SRC  DT = Frame Start
	0x04, 0x50, 0x04, 0x50, 0x40,  // DEST DT = Frame Start
	0x04, 0x50, 0x04, 0x51, 0x01,  // SRC  DT = Frame End
	0x04, 0x50, 0x04, 0x52, 0x41,  // DEST DT = Frame End

	// z map to vc0
	0x04, 0x50, 0x04, 0x8B, 0x07,  // Enable 3 Mappings
	0x04, 0x50, 0x04, 0x8D, 0x2C,  // SRC  0b00101100, DT = 0x2C VC=0
	0x04, 0x50, 0x04, 0x8E, 0x2C,  // DEST 0b01101100, DT = 0x2C VC=0
	0x04, 0x50, 0x04, 0x8F, 0x00,  // SRC  DT = Frame Start
	0x04, 0x50, 0x04, 0x90, 0x00,  // DEST DT = Frame Start
	0x04, 0x50, 0x04, 0x91, 0x01,  // SRC  DT = Frame End
	0x04, 0x50, 0x04, 0x92, 0x01,  // DEST DT = Frame End

	0x04, 0x50, 0x03, 0x25, 0x80,  // wait for a new frame
};

uint8_t max96718_porta_out_setting[] = {
	0x04, 0x50, 0x04, 0x6D, 0x55,  // Pipe Y to dphy1.
	0x04, 0x50, 0x04, 0xAD, 0x55,  // Pipe Z to dphy1.
};

uint8_t max96718_portb_out_setting[] = {
	0x04, 0x50, 0x04, 0x6D, 0xaa,  // Pipe Y to dphy2.
	0x04, 0x50, 0x04, 0xAD, 0xaa,  // Pipe Z to dphy2.
};

uint8_t galaxy_sepa_max96712_csia_reset[] = {
	0x04, 0x52, 0x08, 0xA2, 0xC4,
	0x04, 0x52, 0x08, 0xA2, 0xF4,
};

uint8_t galaxy_sepa_max96712_csib_reset[] = {
	0x04, 0x52, 0x08, 0xA2, 0x34,
	0x04, 0x52, 0x08, 0xA2, 0xF4,
};

uint8_t galaxy_maxser_sensor_i2cmap_setting[] = {
	0x04, 0x80, 0x00, 0x44, 0x32,
	0x04, 0x80, 0x00, 0x45, 0x30,
};

// ovx8b(max9295) + ovx3c(max9295)
uint8_t sensing_with_max96712_max9295_max9295_init_setting[] = {
	// reset 0820
	0x03, 0x50, 0x01, 0x00,
	0x00, 0xff,
	0x03, 0x50, 0x01, 0x1f,
	0x00, 0xff,
	0x04, 0x52, 0x00, 0x13, 0x40, 	// reset all.
	0x00, 0xff,
	0x00, 0xff,
	0x04, 0x52, 0x14, 0x49, 0x75,  // Enable ErrChPwrUp, Enhance link stability
	0x04, 0x52, 0x15, 0x49, 0x75,
	0x04, 0x52, 0x16, 0x49, 0x75,
	0x04, 0x52, 0x17, 0x49, 0x75,

	// solve unlock issue by excessive jitter on the GMSL link over a narrow temperature range
	0x04, 0x52, 0x06, 0xC2, 0x10,

 //         0x04, 0x90, 0x00, 0x01, 0xC9,        //I2C SEL: I2C1
	0x00, 0xff,
	0x04, 0x52, 0x00, 0x11, 0x22,   // Link D:6Gbps C:6Gbps
	0x04, 0x52, 0x00, 0x18, 0x0F, 	// One-shot link reset for all
	0x00, 0xff,
	0x00, 0xff,

	0x04, 0x52, 0x00, 0x06, 0xF8,     // Link D
	0x00, 0xff,
	0x04, 0x80, 0x00, 0x00, 0x82,
	0x04, 0x82, 0x00, 0x42, 0xC4,
	0x04, 0x82, 0x00, 0x43, 0x82,
	0x04, 0x82, 0x00, 0x44, 0x22,
	0x04, 0x82, 0x00, 0x45, 0x6c,

	0x04, 0x52, 0x00, 0x06, 0xF4,     // Link C
	0x00, 0x32,
	0x04, 0x80, 0x00, 0x00, 0x84,
	0x04, 0x84, 0x00, 0x42, 0xC4,
	0x04, 0x84, 0x00, 0x43, 0x84,
	0x04, 0x84, 0x00, 0x44, 0x24,
	0x04, 0x84, 0x00, 0x45, 0x6C,

	0x04, 0x52, 0x00, 0x06, 0xFC,   // Enable 2 Links in GMSL2 mode
	0x00, 0xFF,

	// LinkD: MAX9295 - Serializer config
	0x04, 0x82, 0x00, 0x10, 0x15,
	0x04, 0x82, 0x00, 0x12, 0x14,
	0x04, 0x82, 0x03, 0x11, 0x40,	 // start x/y/z/u from B,40
	0x04, 0x82, 0x03, 0x08, 0x64,	 // x/y/z/u selected B,64
	0x04, 0x82, 0x00, 0x02, 0x43,	 // Video transmit enable  //transmit Z,43

	0x04, 0x82, 0x03, 0x18, 0x6c,

	0x04, 0x82, 0x02, 0xD6, 0x80,
	0x00, 0x20,
	0x04, 0x82, 0x02, 0xD6, 0x9C,
	0x00, 0x20,
	0x04, 0x82, 0x00, 0x58, 0x80,

	// LinkC: MAX96717 - Serializer config
	0x04, 0x84, 0x03, 0x11, 0x40, 	// start z from B,20
	0x04, 0x84, 0x03, 0x08, 0x64, 	// z selected B,62
	0x04, 0x84, 0x00, 0x02, 0x43, 	// Video transmit z enable
	0x04, 0x84, 0x03, 0x18, 0x6c, 	// z dt1: 0x2c

	0x04, 0x84, 0x03, 0xf0, 0x51,
	0x04, 0x84, 0x00, 0x03, 0x03,
	0x04, 0x84, 0x00, 0x06, 0xb1,
	0x04, 0x84, 0x02, 0xbe, 0x18,
	0x04, 0x84, 0x02, 0xbf, 0x60,
	0x04, 0x84, 0x00, 0x58, 0x80, 	// z: tx crc.

	// MAX96712 - Deserializer config
	// Video Pipe Selection
	// 0x04, 0x90, 0x00, 0xF0, 0xAE,  	// pipe0: D-Z, pipie1: C-Z.
	0x04, 0x52, 0x00, 0xF0, 0xAE,  	// pipe0: D-Z, pipie1: C-Z.
	// 0x04, 0x90, 0x00, 0xF1, 0xEA,  	// pipe2: C-Z, pipie3: D-Z.
	// 0x04, 0x90, 0x00, 0xF2, 0x40, 	// pipe4: A-X, pipie5: B-X.
	// 0x04, 0x90, 0x00, 0xF3, 0xC8, 	// pipe6: D-X, pipie7: D-X.
	0x04, 0x52, 0x00, 0xF4, 0x03,  	// Turn on pipe 0+1.
	0x04, 0x52, 0x00, 0x60, 0x44,  	// a/b-z: rx crc.

	// Video Pipe to MIPI Controller Mapping
	// RAW12, video pipe 0
	0x04, 0x52, 0x09, 0x0B, 0x07,  	// pipe0: s/d 0~2 pipe0: CSI-A:VC0.
	0x04, 0x52, 0x09, 0x2D, 0x15,  	// pipe0: s/d 0~2 map to MIPI Controller 1
	0x04, 0x52, 0x09, 0x0D, 0x2C,
	0x04, 0x52, 0x09, 0x0E, 0x2C,  	// pipe0: s/d 0 map data to VC0:RAW12
	0x04, 0x52, 0x09, 0x0F, 0x00,
	0x04, 0x52, 0x09, 0x10, 0x00,  	// pipe0: s/d 1 map FS to VC0
	0x04, 0x52, 0x09, 0x11, 0x01,
	0x04, 0x52, 0x09, 0x12, 0x01,  	// pipe0: s/d 2 map FS to VC0

	0x04, 0x52, 0x09, 0x4B, 0x07,    // Map source 0~2 pipi1: CSI-A: VC1.
	0x04, 0x52, 0x09, 0x6D, 0x15,
	0x04, 0x52, 0x09, 0x4D, 0x2C,
	0x04, 0x52, 0x09, 0x4E, 0x6C,    // vc = 1
	0x04, 0x52, 0x09, 0x4F, 0x00,
	0x04, 0x52, 0x09, 0x50, 0x40,
	0x04, 0x52, 0x09, 0x51, 0x01,
	0x04, 0x52, 0x09, 0x52, 0x41,

	// MIPI PHY Setting
	// Set Des in 2x4 mode
	0x04, 0x52, 0x08, 0xA0, 0x04,
	// Set Lane Mapping for 4-lane port A
	0x04, 0x52, 0x08, 0xA3, 0xE4,
	0x04, 0x52, 0x08, 0xA4, 0xE4,
	// Set 4 lane D-PHY
	0x04, 0x52, 0x09, 0x0A, 0xC0,
	0x04, 0x52, 0x09, 0x4A, 0xC0,
	0x04, 0x52, 0x09, 0x8A, 0xC0,
	0x04, 0x52, 0x09, 0xCA, 0xC0,
	// Turn on MIPI PHYs 0~3
	0x04, 0x52, 0x08, 0xA2, 0xF4,

	// Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
	0x04, 0x52, 0x1C, 0x00, 0xF4,
	0x04, 0x52, 0x1D, 0x00, 0xF4,
	0x04, 0x52, 0x1E, 0x00, 0xF4,
	0x04, 0x52, 0x1F, 0x00, 0xF4,
	// Set Data rate to be 2000Mbps/lane
	// 0x04, 0x90, 0x04, 0x15, 0x34,
	0x04, 0x52, 0x04, 0x18, 0x34,
	0x04, 0x52, 0x04, 0x1B, 0x34,
	// 0x04, 0x90, 0x04, 0x1E, 0x34,
	// Release reset to DPLL (config_soft_rst_n = 1)
	0x04, 0x52, 0x1C, 0x00, 0xF5,
	0x04, 0x52, 0x1D, 0x00, 0xF5,
	0x04, 0x52, 0x1E, 0x00, 0xF5,
	0x04, 0x52, 0x1F, 0x00, 0xF5,
	0x04, 0x52, 0x04, 0x0B, 0x62,  	// stream on
};

uint32_t ovx3c_init_setting_24M[] = {
	/* PLL1:
	 * 24M(REF) / 2 / 1.5 * 200 = 1600M(VCO)
	 * 1600M(VCO) / 6 / 2 = 133.33M(PLL_SYS)
	 * 1600M(VCO) / 4 = 400M(PHYCLK)
	 * 1600M(VCO) / 4 / 4 / 1 = 100M(PCLK)
	 */
	0x0301, 0xc8,
	0x0303, 0x01,
	0x0304, 0x00,
	0x0305, 0xc8,
	0x0307, 0x03,
	0x0306, 0x04,
	/* PLL2:
	 * 24M(REF) / 1 / 4 * 300 = 1800M(VCO)
	 * 1600M(VCO) / 5 / 4 = 90M(SCLK)
	 */
	0x0323, 0x05,
	0x0324, 0x01,
	0x0325, 0x2c,
};

uint32_t ovx3c_init_setting_27M[] = {
	/* PLL1:
	 * 24M(REF) / 2 / 1.5 * 200 = 1600M(VCO)
	 * 1600M(VCO) / 6 / 2 = 133.33M(PLL_SYS)
	 * 1600M(VCO) / 4 = 400M(PHYCLK)
	 * 1600M(VCO) / 4 / 4 / 1 = 100M(PCLK)
	 */
	0x0301, 0x88,
	0x0303, 0x05,
	0x0304, 0x00,
	0x0305, 0xed,
	0x0307, 0x03,
	0x0306, 0x04,
	/* PLL2:
	 * 27M(REF) / 1 / 3 * 200 = 1800M(VCO)
	 * 1600M(VCO) / 5 / 4 = 90M(SCLK)
	 */
	0x0323, 0x04,
	0x0324, 0x00,
	0x0325, 0xc8,
};

uint32_t ovx3c_init_setting_1280p_30fps[] = {
	0x380c, 0x08,
	0x380d, 0x8e,
	0x384c, 0x04,
	0x384d, 0x1a,
	0x388c, 0x03,
	0x388d, 0x4a,
	0x380e, 0x02,
	0x380f, 0xdf,

	// white noise problem
	0x5d46, 0x00,
	0x5d47, 0xcd,
	0x5d48, 0x00,
	0x5d49, 0xd1,
};

uint32_t ovx3c_init_setting_1280p_25fps[] = {
	0x380c, 0x08,
	0x380d, 0x8e,
	0x384c, 0x04,
	0x384d, 0x1a,
	0x388c, 0x03,
	0x388d, 0x4a,
	0x380e, 0x03,
	0x380f, 0x72,

	// white noise problem
	0x5d46, 0x00,
	0x5d47, 0xcd,
	0x5d48, 0x00,
	0x5d49, 0xd1,
};

uint32_t ovx3c_init_setting_1280p_20fps[] = {
	0x380c, 0x0c,
	0x380d, 0xd5,
	0x384c, 0x06,
	0x384d, 0x27,
	0x388c, 0x06,
	0x388d, 0x7e,
	0x380e, 0x02,
	0x380f, 0xb2,

	// white noise problem
	0x5d46, 0x00,
	0x5d47, 0x88,
	0x5d48, 0x00,
	0x5d49, 0x8c,
};

uint32_t ovx3c_init_setting_1280p_10fps[] = {
	0x380c, 0x0c,
	0x380d, 0xd5,
	0x384c, 0x06,
	0x384d, 0x27,
	0x388c, 0x06,
	0x388d, 0x7e,
	0x380e, 0x05,
	0x380f, 0x64,

	// white noise problem
	0x5d46, 0x00,
	0x5d47, 0x88,
	0x5d48, 0x00,
	0x5d49, 0x8c,
};

uint32_t ovx3c_init_setting_1280p_15fps[] = {
	0x380c, 0x0c,
	0x380d, 0xd5,
	0x384c, 0x06,
	0x384d, 0x27,
	0x388c, 0x06,
	0x388d, 0x7e,
	0x380e, 0x03,
	0x380f, 0x98,

	// white noise problem
	0x5d46, 0x00,
	0x5d47, 0x88,
	0x5d48, 0x00,
	0x5d49, 0x8c,
};

uint32_t ovx3c_init_setting_rst[] = {
	0x3208, 0x10,  // group hold end
	0x3211, 0x40,  // manual lunch on, group hold crc enable
	0x3208, 0xA0,  // delay lunch
	0x0100, 0x00,  // stream off
	0x0103, 0x01,  // software rst
	0x0107, 0x01,  // software rst
};

uint32_t ovx3c_init_setting_hdr4[] = {
	//  @@ X3C_1920x1280_30fps_HDR4_LFR_PWL12_mipi400
	//  Version ae_04
	0x4d5a, 0x1a,
	0x4d09, 0xff,
	0x4d09, 0xdf,
	0x3208, 0x04,
	0x4620, 0x04,
	0x3208, 0x14,
	0x3208, 0x05,
	0x4620, 0x04,
	0x3208, 0x15,
	0x3208, 0x02,
	0x3507, 0x00,
	0x3208, 0x12,
	0x3208, 0xa2,
	0x0301, 0xc8,
	0x0303, 0x01,
	0x0304, 0x00,    // 01
	0x0305, 0xc8,    // 2c
	0x0306, 0x04,
	0x0307, 0x03,    // 01
	0x0316, 0x00,
	0x0317, 0x00,
	0x0318, 0x00,
	0x0323, 0x05,
	0x0324, 0x01,
	0x0325, 0x2c,
	0x0400, 0xe0,
	0x0401, 0x80,
	0x0403, 0xde,
	0x0404, 0x34,
	0x0405, 0x3b,
	0x0406, 0xde,
	0x0407, 0x08,
	0x0408, 0xe0,
	0x0409, 0x20,  //  7f  pll monitor reg expect
	0x040a, 0x1b,  //  de
	0x040b, 0xdb,  //  34
	0x040c, 0xd7,  //  47
	0x040d, 0x29,  //  d8
	0x040e, 0x07,  //  08
	0x2803, 0xfe,
	0x280b, 0x00,
	0x280c, 0x79,
	0x3001, 0x03,
	0x3002, 0xf8,
	0x3005, 0x80,
	0x3007, 0x01,
	0x3008, 0x80,
	0x3012, 0x41,
	0x3020, 0x05,
	0x3700, 0x28,
	0x3701, 0x15,
	0x3702, 0x19,
	0x3703, 0x23,
	0x3704, 0x0a,
	0x3705, 0x00,
	0x3706, 0x3e,
	0x3707, 0x0d,
	0x3708, 0x50,
	0x3709, 0x5a,
	0x370a, 0x00,
	0x370b, 0x96,
	0x3711, 0x11,
	0x3712, 0x13,
	0x3717, 0x02,
	0x3718, 0x73,
	0x372c, 0x40,
	0x3733, 0x01,
	0x3738, 0x36,
	0x3739, 0x36,
	0x373a, 0x25,
	0x373b, 0x25,
	0x373f, 0x21,
	0x3740, 0x21,
	0x3741, 0x21,
	0x3742, 0x21,
	0x3747, 0x28,
	0x3748, 0x28,
	0x3749, 0x19,
	0x3755, 0x1a,
	0x3756, 0x0a,
	0x3757, 0x1c,
	0x3765, 0x19,
	0x3766, 0x05,
	0x3767, 0x05,
	0x3768, 0x13,
	0x376c, 0x07,
	0x3778, 0x20,
	0x377c, 0xc8,
	0x3781, 0x02,
	0x3783, 0x02,
	0x379c, 0x58,
	0x379e, 0x00,
	0x379f, 0x00,
	0x37a0, 0x00,
	0x37bc, 0x22,
	0x37c0, 0x01,
	0x37c4, 0x3e,
	0x37c5, 0x3e,
	0x37c6, 0x2a,
	0x37c7, 0x28,
	0x37c8, 0x02,
	0x37c9, 0x12,
	0x37cb, 0x29,
	0x37cd, 0x29,
	0x37d2, 0x00,
	0x37d3, 0x73,
	0x37d6, 0x00,
	0x37d7, 0x6b,
	0x37dc, 0x00,
	0x37df, 0x54,
	0x37e2, 0x00,
	0x37e3, 0x00,
	0x37f8, 0x00,
	0x37f9, 0x01,
	0x37fa, 0x00,
	0x37fb, 0x19,
	0x3c03, 0x01,
	0x3c04, 0x01,
	0x3c06, 0x21,
	0x3c08, 0x01,
	0x3c09, 0x01,
	0x3c0a, 0x01,
	0x3c0b, 0x21,
	0x3c13, 0x21,
	0x3c14, 0x82,
	0x3c16, 0x13,
	0x3c21, 0x00,
	0x3c22, 0xf3,
	0x3c37, 0x12,
	0x3c38, 0x31,
	0x3c3c, 0x00,
	0x3c3d, 0x03,
	0x3c44, 0x16,
	0x3c5c, 0x8a,
	0x3c5f, 0x03,
	0x3c61, 0x80,
	0x3c6f, 0x2b,
	0x3c70, 0x5f,
	0x3c71, 0x2c,
	0x3c72, 0x2c,
	0x3c73, 0x2c,
	0x3c76, 0x12,
	0x3182, 0x12,
	0x320e, 0x00,
	0x320f, 0x00,
	0x3211, 0x61,
	0x3215, 0xcd,
	0x3219, 0x08,
	0x3506, 0x30,
	0x350a, 0x01,
	0x350b, 0x00,
	0x350c, 0x00,
	0x3586, 0x60,
	0x358a, 0x01,
	0x358b, 0x00,
	0x358c, 0x00,
	0x3541, 0x00,
	0x3542, 0x04,
	0x3548, 0x04,
	0x3549, 0x40,
	0x354a, 0x01,
	0x354b, 0x00,
	0x354c, 0x00,
	0x35c1, 0x00,
	0x35c2, 0x02,
	0x35c6, 0xa0,
	0x3600, 0x8f,
	0x3605, 0x16,
	0x3609, 0xf0,
	0x360a, 0x01,
	0x360e, 0x1d,
	0x360f, 0x10,
	0x3610, 0x70,
	0x3611, 0x3a,
	0x3612, 0x28,
	0x361a, 0x29,
	0x361b, 0x6c,
	0x361c, 0x0b,
	0x361d, 0x00,
	0x361e, 0xfc,
	0x362a, 0x00,
	0x364d, 0x0f,
	0x364e, 0x18,
	0x364f, 0x12,
	0x3653, 0x1c,
	0x3654, 0x00,
	0x3655, 0x1f,
	0x3656, 0x1f,
	0x3657, 0x0c,
	0x3658, 0x0a,
	0x3659, 0x14,
	0x365a, 0x18,
	0x365b, 0x14,
	0x365c, 0x10,
	0x365e, 0x12,
	0x3674, 0x08,
	0x3677, 0x3a,
	0x3678, 0x3a,
	0x3679, 0x19,
	0x3802, 0x00,
	0x3803, 0x04,
	0x3806, 0x05,
	0x3807, 0x0b,
	0x3808, 0x07,    // X size high
	0x3809, 0x80,    // X size low
	0x380a, 0x05,    // Y size high 05
	0x380b, 0x00,    // Y size low 00
	0x380c, 0x04,    // Linelength high
	0x380d, 0x47,    // Linelength low
	0x380e, 0x02,    // Framelength high
	0x380f, 0xae,    // Framelength low
	0x3810, 0x00,
	0x3811, 0x08,
	0x3812, 0x00,
	0x3813, 0x04,
	0x3816, 0x01,
	0x3817, 0x01,
	0x381c, 0x18,
	0x381e, 0x01,
	0x381f, 0x01,
	0x3820, 0x20,    // mirror enable
	0x3821, 0x19,
	0x3832, 0x00,
	0x3834, 0x00,
	0x384c, 0x02,
	0x384d, 0x0d,
	0x3850, 0x00,
	0x3851, 0x42,
	0x3852, 0x00,
	0x3853, 0x40,
	0x3858, 0x04,
	0x388c, 0x02,
	0x388d, 0x2b,
	0x3b40, 0x05,
	0x3b41, 0x40,
	0x3b42, 0x00,
	0x3b43, 0x90,
	0x3b44, 0x00,
	0x3b45, 0x20,
	0x3b46, 0x00,
	0x3b47, 0x20,
	0x3b48, 0x19,
	0x3b49, 0x12,
	0x3b4a, 0x16,
	0x3b4b, 0x2e,
	0x3b4c, 0x00,
	0x3b4d, 0x00,
	0x3b86, 0x00,
	0x3b87, 0x34,
	0x3b88, 0x00,
	0x3b89, 0x08,
	0x3b8a, 0x05,
	0x3b8b, 0x00,
	0x3b8c, 0x07,
	0x3b8d, 0x80,
	0x3b8e, 0x00,
	0x3b8f, 0x00,
	0x3b92, 0x05,
	0x3b93, 0x00,
	0x3b94, 0x07,
	0x3b95, 0x80,
	0x3b9e, 0x09,
	0x3d85, 0x05,  //  07 automatic load setting disable
	0x3d8a, 0x03,
	0x3d8b, 0xff,
	0x3d99, 0x00,
	0x3d9a, 0x9f,
	0x3d9b, 0x00,
	0x3d9c, 0xa0,
	0x3da4, 0x00,
	0x3da7, 0x50,
	0x420e, 0x6b,
	0x420f, 0x6e,
	0x4210, 0x06,
	0x4211, 0xc1,
	0x421e, 0x02,
	0x421f, 0x45,
	0x4220, 0xe1,
	0x4221, 0x01,
	0x4301, 0xff,
	0x4307, 0x03,
	0x4308, 0x13,
	0x430a, 0x13,
	0x430d, 0x13,  //  93-----12 13 embed type bit7->MIPI top emb same as image
	0x430f, 0x57,
	0x4310, 0x95,
	0x4311, 0x16,
	0x4316, 0x00,
	0x4317, 0x38,
	0x4319, 0x03,
	0x431a, 0x00,
	0x431b, 0x00,
	0x431d, 0x2a,
	0x431e, 0x11,
	0x431f, 0x20,
	0x4320, 0x19,
	0x4323, 0x80,
	0x4324, 0x00,
	0x4503, 0x4e,
	0x4505, 0x00,
	0x4509, 0x00,
	0x450a, 0x00,
	0x4580, 0xf8,
	0x4583, 0x07,
	0x4584, 0x6a,
	0x4585, 0x08,
	0x4586, 0x05,
	0x4587, 0x04,
	0x4588, 0x73,
	0x4589, 0x05,
	0x458a, 0x1f,
	0x458b, 0x02,
	0x458c, 0xdc,
	0x458d, 0x03,
	0x458e, 0x02,
	0x4597, 0x07,
	0x4598, 0x40,
	0x4599, 0x0e,
	0x459a, 0x0e,
	0x459b, 0xfb,
	0x459c, 0xf3,
	0x4602, 0x00,
	0x4603, 0x13,
	0x4604, 0x00,
	0x4609, 0x0a,
	0x460a, 0x30,
	0x4610, 0x00,
	0x4611, 0x70,
	0x4612, 0x01,
	0x4613, 0x00,
	0x4614, 0x00,
	0x4615, 0x70,
	0x4616, 0x01,
	0x4617, 0x00,
	0x4800, 0x04,
	0x480a, 0x22,
	0x4813, 0xe4,
	0x4814, 0x2a,
	0x4837, 0x28,    // 0d
	0x484b, 0x47,
	0x484f, 0x00,
	0x4887, 0x51,
	0x4d00, 0x4a,
	0x4d01, 0x18,
	0x4d05, 0xff,
	0x4d06, 0x88,
	0x4d08, 0x63,
	0x4d09, 0xdf,
	0x4d15, 0x7d,
	0x4d1a, 0x20,
	0x4d30, 0x0a,
	0x4d31, 0x00,
	0x4d34, 0x7d,
	0x4d3c, 0x7d,
	0x4f00, 0x00,
	0x4f01, 0x00,
	0x4f02, 0x00,
	0x4f03, 0x20,
	0x4f04, 0xe0,
	0x6a00, 0x00,
	0x6a01, 0x20,
	0x6a02, 0x00,
	0x6a03, 0x20,
	0x6a04, 0x02,
	0x6a05, 0x80,
	0x6a06, 0x01,
	0x6a07, 0xe0,
	0x6a08, 0xcf,
	0x6a09, 0x01,
	0x6a0a, 0x40,
	0x6a20, 0x00,
	0x6a21, 0x02,
	0x6a22, 0x00,
	0x6a23, 0x00,
	0x6a24, 0x00,
	0x6a25, 0x00,
	0x6a26, 0x00,
	0x6a27, 0x00,
	0x6a28, 0x00,
	0x5000, 0x8f,
	0x5001, 0x75,
	0x5002, 0x7f,
	0x5003, 0x7a,
	0x5004, 0x3e,
	0x5005, 0x1e,
	0x5006, 0x1e,
	0x5007, 0x1e,
	0x5008, 0x00,
	0x500c, 0x00,
	0x502c, 0x00,
	0x502e, 0x00,
	0x502f, 0x00,
	0x504b, 0x00,
	0x5053, 0x00,
	0x505b, 0x00,
	0x5063, 0x00,
	0x5070, 0x00,
	0x5074, 0x04,
	0x507a, 0x04,
	0x507b, 0x09,
	0x5500, 0x02,
	0x5700, 0x02,
	0x5900, 0x02,
	0x6007, 0x04,
	0x6008, 0x05,
	0x6009, 0x02,
	0x600b, 0x08,
	0x600c, 0x07,
	0x600d, 0x88,
	0x6016, 0x00,
	0x6027, 0x04,
	0x6028, 0x05,
	0x6029, 0x02,
	0x602b, 0x08,
	0x602c, 0x07,
	0x602d, 0x88,
	0x6047, 0x04,
	0x6048, 0x05,
	0x6049, 0x02,
	0x604b, 0x08,
	0x604c, 0x07,
	0x604d, 0x88,
	0x6067, 0x04,
	0x6068, 0x05,
	0x6069, 0x02,
	0x606b, 0x08,
	0x606c, 0x07,
	0x606d, 0x88,
	0x6087, 0x04,
	0x6088, 0x05,
	0x6089, 0x02,
	0x608b, 0x08,
	0x608c, 0x07,
	0x608d, 0x88,

	0x5240, 0x0f,
	0x5243, 0x00,
	0x5244, 0x00,
	0x5245, 0x00,
	0x5246, 0x00,
	0x5247, 0x00,
	0x5248, 0x00,
	0x5249, 0x00,
	0x5440, 0x0f,
	0x5443, 0x00,
	0x5445, 0x00,
	0x5447, 0x00,
	0x5448, 0x00,
	0x5449, 0x00,
	0x5640, 0x0f,
	0x5642, 0x00,
	0x5643, 0x00,
	0x5644, 0x00,
	0x5645, 0x00,
	0x5646, 0x00,
	0x5647, 0x00,
	0x5649, 0x00,
	0x5840, 0x0f,
	0x5842, 0x00,
	0x5843, 0x00,
	0x5845, 0x00,
	0x5846, 0x00,
	0x5847, 0x00,
	0x5848, 0x00,
	0x5849, 0x00,
	0x4001, 0x2b,
	0x4008, 0x02,  //  zero line start row
	0x4009, 0x03,  //  zero line end row
	0x4018, 0x12,
	0x4022, 0x40,
	0x4023, 0x20,
	0x4026, 0x00,
	0x4027, 0x40,
	0x4028, 0x00,
	0x4029, 0x40,
	0x402a, 0x00,
	0x402b, 0x40,
	0x402c, 0x00,
	0x402d, 0x40,
	0x405e, 0x00,
	0x405f, 0x00,
	0x4060, 0x00,
	0x4061, 0x00,
	0x4062, 0x00,
	0x4063, 0x00,
	0x4064, 0x00,
	0x4065, 0x00,
	0x4066, 0x00,
	0x4067, 0x00,
	0x4068, 0x00,
	0x4069, 0x00,
	0x406a, 0x00,
	0x406b, 0x00,
	0x406c, 0x00,
	0x406d, 0x00,
	0x406e, 0x00,
	0x406f, 0x00,
	0x4070, 0x00,
	0x4071, 0x00,
	0x4072, 0x00,
	0x4073, 0x00,
	0x4074, 0x00,
	0x4075, 0x00,
	0x4076, 0x00,
	0x4077, 0x00,
	0x4078, 0x00,
	0x4079, 0x00,
	0x407a, 0x00,
	0x407b, 0x00,
	0x407c, 0x00,
	0x407d, 0x00,
	0x407e, 0xcc,
	0x407f, 0x18,
	0x4080, 0xff,
	0x4081, 0xff,
	0x4082, 0x01,
	0x4083, 0x53,
	0x4084, 0x01,
	0x4085, 0x2b,
	0x4086, 0x00,
	0x4087, 0xb3,
	0x4640, 0x41,  //  0x40  uid_mirror -> mirror enable
	0x4641, 0x11,
	0x4642, 0x0e,
	0x4643, 0xee,
	0x4646, 0x0f,
	0x4648, 0x00,
	0x4649, 0x03,
	0x4f04, 0xf8,
	0x4d09, 0xff,
	0x4d09, 0xdf,
	0x5019, 0x00,
	0x501a, 0xff,
	0x501b, 0xff,
	0x501d, 0x00,
	0x501e, 0x23,
	0x501f, 0x8e,
	0x5021, 0x00,
	0x5022, 0x00,
	0x5023, 0x50,
	0x5025, 0x00,
	0x5026, 0x23,
	0x5027, 0x8e,
	0x5003, 0x7a,
	0x5b80, 0x08,
	0x5c00, 0x08,
	0x5c80, 0x00,
	0x5bbe, 0x12,
	0x5c3e, 0x12,
	0x5cbe, 0x12,
	0x5b8a, 0x80,
	0x5b8b, 0x80,
	0x5b8c, 0x80,
	0x5b8d, 0x80,
	0x5b8e, 0x60,  //  combine ispx ctrl
	0x5b8f, 0x80,
	0x5b90, 0x80,
	0x5b91, 0x80,
	0x5b92, 0x80,
	0x5b93, 0x20,
	0x5b94, 0x80,
	0x5b95, 0x80,
	0x5b96, 0x80,
	0x5b97, 0x20,
	0x5b98, 0x00,
	0x5b99, 0x80,
	0x5b9a, 0x40,
	0x5b9b, 0x20,
	0x5b9c, 0x00,
	0x5b9d, 0x00,
	0x5b9e, 0x80,
	0x5b9f, 0x00,
	0x5ba0, 0x00,
	0x5ba1, 0x00,
	0x5ba2, 0x00,
	0x5ba3, 0x00,
	0x5ba4, 0x00,
	0x5ba5, 0x00,
	0x5ba6, 0x00,
	0x5ba7, 0x00,
	0x5ba8, 0x02,
	0x5ba9, 0x00,
	0x5baa, 0x02,
	0x5bab, 0x76,
	0x5bac, 0x03,
	0x5bad, 0x08,
	0x5bae, 0x00,
	0x5baf, 0x80,
	0x5bb0, 0x00,
	0x5bb1, 0xc0,
	0x5bb2, 0x01,
	0x5bb3, 0x00,
	0x5c0a, 0x80,
	0x5c0b, 0x80,
	0x5c0c, 0x80,
	0x5c0d, 0x80,
	0x5c0e, 0x60,
	0x5c0f, 0x80,
	0x5c10, 0x80,
	0x5c11, 0x80,
	0x5c12, 0x60,
	0x5c13, 0x20,
	0x5c14, 0x80,
	0x5c15, 0x80,
	0x5c16, 0x80,
	0x5c17, 0x20,
	0x5c18, 0x00,
	0x5c19, 0x80,
	0x5c1a, 0x40,
	0x5c1b, 0x20,
	0x5c1c, 0x00,
	0x5c1d, 0x00,
	0x5c1e, 0x80,
	0x5c1f, 0x00,
	0x5c20, 0x00,
	0x5c21, 0x00,
	0x5c22, 0x00,
	0x5c23, 0x00,
	0x5c24, 0x00,
	0x5c25, 0x00,
	0x5c26, 0x00,
	0x5c27, 0x00,
	0x5c28, 0x02,
	0x5c29, 0x00,
	0x5c2a, 0x02,
	0x5c2b, 0x76,
	0x5c2c, 0x03,
	0x5c2d, 0x08,
	0x5c2e, 0x00,
	0x5c2f, 0x80,
	0x5c30, 0x00,
	0x5c31, 0xc0,
	0x5c32, 0x01,
	0x5c33, 0x00,
	0x5c8a, 0x80,
	0x5c8b, 0x80,
	0x5c8c, 0x80,
	0x5c8d, 0x80,
	0x5c8e, 0x80,
	0x5c8f, 0x80,
	0x5c90, 0x80,
	0x5c91, 0x80,
	0x5c92, 0x80,
	0x5c93, 0x60,
	0x5c94, 0x80,
	0x5c95, 0x80,
	0x5c96, 0x80,
	0x5c97, 0x60,
	0x5c98, 0x40,
	0x5c99, 0x80,
	0x5c9a, 0x80,
	0x5c9b, 0x80,
	0x5c9c, 0x40,
	0x5c9d, 0x20,
	0x5c9e, 0x80,
	0x5c9f, 0x80,
	0x5ca0, 0x80,
	0x5ca1, 0x20,
	0x5ca2, 0x00,
	0x5ca3, 0x80,
	0x5ca4, 0x80,
	0x5ca5, 0x80,
	0x5ca6, 0x00,
	0x5ca7, 0x00,
	0x5ca8, 0x01,
	0x5ca9, 0x00,
	0x5caa, 0x02,
	0x5cab, 0x00,
	0x5cac, 0x03,
	0x5cad, 0x08,
	0x5cae, 0x01,
	0x5caf, 0x00,
	0x5cb0, 0x02,
	0x5cb1, 0x00,
	0x5cb2, 0x03,
	0x5cb3, 0x08,
	0x5be7, 0x80,
	0x5bc9, 0x80,
	0x5bca, 0x80,
	0x5bcb, 0x80,
	0x5bcc, 0x80,
	0x5bcd, 0x80,
	0x5bce, 0x80,
	0x5bcf, 0x80,
	0x5bd0, 0x80,
	0x5bd1, 0x80,
	0x5bd2, 0x20,
	0x5bd3, 0x80,
	0x5bd4, 0x40,
	0x5bd5, 0x20,
	0x5bd6, 0x00,
	0x5bd7, 0x00,
	0x5bd8, 0x00,
	0x5bd9, 0x00,
	0x5bda, 0x00,
	0x5bdb, 0x00,
	0x5bdc, 0x00,
	0x5bdd, 0x00,
	0x5bde, 0x00,
	0x5bdf, 0x00,
	0x5be0, 0x00,
	0x5be1, 0x00,
	0x5be2, 0x00,
	0x5be3, 0x00,
	0x5be4, 0x00,
	0x5be5, 0x00,
	0x5be6, 0x00,
	0x5c49, 0x80,
	0x5c4a, 0x80,
	0x5c4b, 0x80,
	0x5c4c, 0x80,
	0x5c4d, 0x40,
	0x5c4e, 0x80,
	0x5c4f, 0x80,
	0x5c50, 0x80,
	0x5c51, 0x60,
	0x5c52, 0x20,
	0x5c53, 0x80,
	0x5c54, 0x80,
	0x5c55, 0x80,
	0x5c56, 0x20,
	0x5c57, 0x00,
	0x5c58, 0x80,
	0x5c59, 0x40,
	0x5c5a, 0x20,
	0x5c5b, 0x00,
	0x5c5c, 0x00,
	0x5c5d, 0x80,
	0x5c5e, 0x00,
	0x5c5f, 0x00,
	0x5c60, 0x00,
	0x5c61, 0x00,
	0x5c62, 0x00,
	0x5c63, 0x00,
	0x5c64, 0x00,
	0x5c65, 0x00,
	0x5c66, 0x00,
	0x5cc9, 0x80,
	0x5cca, 0x80,
	0x5ccb, 0x80,
	0x5ccc, 0x80,
	0x5ccd, 0x80,
	0x5cce, 0x80,
	0x5ccf, 0x80,
	0x5cd0, 0x80,
	0x5cd1, 0x80,
	0x5cd2, 0x60,
	0x5cd3, 0x80,
	0x5cd4, 0x80,
	0x5cd5, 0x80,
	0x5cd6, 0x60,
	0x5cd7, 0x40,
	0x5cd8, 0x80,
	0x5cd9, 0x80,
	0x5cda, 0x80,
	0x5cdb, 0x40,
	0x5cdc, 0x20,
	0x5cdd, 0x80,
	0x5cde, 0x80,
	0x5cdf, 0x80,
	0x5ce0, 0x20,
	0x5ce1, 0x00,
	0x5ce2, 0x80,
	0x5ce3, 0x80,
	0x5ce4, 0x80,
	0x5ce5, 0x00,
	0x5ce6, 0x00,
	0x5b84, 0x02,
	0x5b85, 0xcc,
	0x5bb4, 0x05,
	0x5bb5, 0xc6,
	0x5c04, 0x02,
	0x5c05, 0xcc,
	0x5c34, 0x05,
	0x5c35, 0x33,
	0x5c84, 0x02,
	0x5c85, 0xcc,
	0x5cb4, 0x05,
	0x5cb5, 0x33,
	0x5bbf, 0x00,
	0x5bc0, 0x04,
	0x5bc1, 0x06,
	0x5bc2, 0xff,
	0x5bc3, 0x00,
	0x5bc4, 0x04,
	0x5bc5, 0x02,
	0x5bc6, 0xb8,
	0x5c3f, 0x00,
	0x5c40, 0x04,
	0x5c41, 0x07,
	0x5c42, 0xff,
	0x5c43, 0x00,
	0x5c44, 0x04,
	0x5c45, 0x03,
	0x5c46, 0xb8,
	0x5cbf, 0x00,
	0x5cc0, 0x20,
	0x5cc1, 0x07,
	0x5cc2, 0xff,
	0x5cc3, 0x00,
	0x5cc4, 0x20,
	0x5cc5, 0x03,
	0x5cc6, 0x00,
	0x5b86, 0x05,
	0x5c06, 0x05,
	0x5c86, 0x05,
	0x5bb8, 0x01,
	0x5bb9, 0x01,
	0x5c38, 0x01,
	0x5c39, 0x01,
	0x5cb8, 0x01,
	0x5cb9, 0x01,
	0x5bc7, 0x00,
	0x5bc8, 0x80,
	0x5c47, 0x00,
	0x5c48, 0x80,
	0x5cc7, 0x00,
	0x5cc8, 0x80,
	0x5bba, 0x01,
	0x5bbb, 0x00,
	0x5c3a, 0x01,
	0x5c3b, 0x00,
	0x5cba, 0x01,
	0x5cbb, 0x00,
	0x5d74, 0x01,
	0x5d75, 0x00,
	0x5d1f, 0x81,
	0x5d11, 0x00,
	0x5d12, 0x10,
	0x5d13, 0x10,
	0x5d15, 0x05,
	0x5d16, 0x05,
	0x5d17, 0x05,
	0x5d08, 0x03,
	0x5d09, 0x6b,
	0x5d0a, 0x03,
	0x5d0b, 0x6b,
	0x5d18, 0x03,
	0x5d19, 0x6b,
	0x5b40, 0x01,
	0x5b41, 0x00,
	0x5b42, 0x00,
	0x5b43, 0x00,
	0x5b44, 0x00,
	0x5b45, 0x00,
	0x5b46, 0x00,
	0x5b47, 0x00,
	0x5b48, 0x01,
	0x5b49, 0x00,
	0x5b4a, 0x00,
	0x5b4b, 0x00,
	0x5b4c, 0x00,
	0x5b4d, 0x00,
	0x5b4e, 0x00,
	0x5b4f, 0x00,
	0x5b50, 0x01,
	0x5b51, 0x00,
	0x5b52, 0x01,
	0x5b53, 0x00,
	0x5b54, 0x00,
	0x5b55, 0x00,
	0x5b56, 0x00,
	0x5b57, 0x00,
	0x5b58, 0x00,
	0x5b59, 0x00,
	0x5b5a, 0x01,
	0x5b5b, 0x00,
	0x5b5c, 0x00,
	0x5b5d, 0x00,
	0x5b5e, 0x00,
	0x5b5f, 0x00,
	0x5b60, 0x00,
	0x5b61, 0x00,
	0x5b62, 0x01,
	0x5b63, 0x00,
	0x5b64, 0x01,
	0x5b65, 0x00,
	0x5b66, 0x00,
	0x5b67, 0x00,
	0x5b68, 0x00,
	0x5b69, 0x00,
	0x5b6a, 0x00,
	0x5b6b, 0x00,
	0x5b6c, 0x01,
	0x5b6d, 0x00,
	0x5b6e, 0x00,
	0x5b6f, 0x00,
	0x5b70, 0x00,
	0x5b71, 0x00,
	0x5b72, 0x00,
	0x5b73, 0x00,
	0x5b74, 0x01,
	0x5b75, 0x00,
	0x5b78, 0x00,
	0x5b79, 0x4c,
	0x5b7a, 0x00,
	0x5b7b, 0xb9,
	0x5b7c, 0x01,
	0x5b7d, 0x38,
	0x5b7e, 0x01,
	0x5280, 0x04,
	0x5281, 0x00,
	0x5282, 0x04,
	0x5283, 0x00,
	0x5284, 0x04,
	0x5285, 0x00,
	0x5286, 0x04,
	0x5287, 0x00,
	0x5480, 0x04,
	0x5481, 0x00,
	0x5482, 0x04,
	0x5483, 0x00,
	0x5484, 0x04,
	0x5485, 0x00,
	0x5486, 0x04,
	0x5487, 0x00,
	0x5680, 0x04,
	0x5681, 0x00,
	0x5682, 0x04,
	0x5683, 0x00,
	0x5684, 0x04,
	0x5685, 0x00,
	0x5686, 0x04,
	0x5687, 0x00,
	0x5880, 0x04,
	0x5881, 0x00,
	0x5882, 0x04,
	0x5883, 0x00,
	0x5884, 0x04,
	0x5885, 0x00,
	0x5886, 0x04,
	0x5887, 0x00,
	0x52c6, 0x00,
	0x52c7, 0x12,
	0x52c8, 0x04,
	0x52c9, 0x02,
	0x52ca, 0x01,
	0x52cb, 0x01,
	0x52cc, 0x04,
	0x52cd, 0x02,
	0x52ce, 0x01,
	0x52cf, 0x01,
	0x52d0, 0x03,
	0x52d1, 0x08,
	0x52d2, 0x0c,
	0x54c6, 0x00,
	0x54c7, 0x12,
	0x54c8, 0x04,
	0x54c9, 0x02,
	0x54ca, 0x01,
	0x54cb, 0x01,
	0x54cc, 0x04,
	0x54cd, 0x02,
	0x54ce, 0x01,
	0x54cf, 0x01,
	0x54d0, 0x03,
	0x54d1, 0x08,
	0x54d2, 0x0c,
	0x56c6, 0x00,
	0x56c7, 0x12,
	0x56c8, 0x04,
	0x56c9, 0x02,
	0x56ca, 0x01,
	0x56cb, 0x01,
	0x56cc, 0x04,
	0x56cd, 0x02,
	0x56ce, 0x01,
	0x56cf, 0x01,
	0x56d0, 0x03,
	0x56d1, 0x08,
	0x56d2, 0x0c,
	0x58c6, 0x00,
	0x58c7, 0x12,
	0x58c8, 0x04,
	0x58c9, 0x02,
	0x58ca, 0x01,
	0x58cb, 0x01,
	0x58cc, 0x04,
	0x58cd, 0x02,
	0x58ce, 0x01,
	0x58cf, 0x01,
	0x58d0, 0x03,
	0x58d1, 0x08,
	0x58d2, 0x0c,
	0x5004, 0x1e,
	0x610a, 0x07,
	0x610b, 0x80,
	0x610c, 0x05,
	0x610d, 0x00,
	0x6102, 0x3f,
	0x6120, 0x75,
	0x6121, 0x75,
	0x6122, 0x75,
	0x6123, 0x75,
	0x6124, 0x75,
	0x6125, 0x75,
	0x6126, 0x75,
	0x6127, 0x75,
	0x6128, 0x75,
	0x6129, 0x75,
	0x612a, 0x75,
	0x612b, 0x75,
	0x612c, 0x75,
	0x612d, 0x75,
	0x612e, 0x75,
	0x612f, 0x75,
	0x6130, 0x75,
	0x6131, 0x75,
	0x6132, 0x75,
	0x6133, 0x75,
	0x6134, 0x75,
	0x6135, 0x75,
	0x6136, 0x75,
	0x6137, 0x75,
	0x6138, 0x75,
	0x6139, 0x75,
	0x613a, 0x75,
	0x613b, 0x75,
	0x613c, 0x75,
	0x613d, 0x75,
	0x613e, 0x75,
	0x613f, 0x75,
	0x6140, 0x75,
	0x6141, 0x75,
	0x6142, 0x75,
	0x6143, 0x75,
	0x6144, 0x75,
	0x6145, 0x75,
	0x6146, 0x75,
	0x6147, 0x75,
	0x6148, 0x75,
	0x6149, 0x75,
	0x614a, 0x75,
	0x614b, 0x75,
	0x614c, 0x75,
	0x614d, 0x75,
	0x614e, 0x75,
	0x614f, 0x75,
	0x6150, 0x75,
	0x6151, 0x75,
	0x6152, 0x75,
	0x6153, 0x75,
	0x6154, 0x75,
	0x6155, 0x75,
	0x6156, 0x75,
	0x6157, 0x75,
	0x6158, 0x75,
	0x6159, 0x75,
	0x615a, 0x75,
	0x615b, 0x75,
	0x615c, 0x75,
	0x615d, 0x75,
	0x615e, 0x75,
	0x615f, 0x75,
	0x6160, 0x75,
	0x6161, 0x75,
	0x6162, 0x75,
	0x6163, 0x75,
	0x6164, 0x75,
	0x6165, 0x75,
	0x6166, 0x75,
	0x6167, 0x75,
	0x6168, 0x75,
	0x6169, 0x75,
	0x616a, 0x75,
	0x616b, 0x75,
	0x616c, 0x75,
	0x616d, 0x75,
	0x616e, 0x75,
	0x616f, 0x75,
	0x6170, 0x75,
	0x6171, 0x75,
	0x6172, 0x75,
	0x6173, 0x75,
	0x6174, 0x75,
	0x6175, 0x75,
	0x6176, 0x75,
	0x6177, 0x75,
	0x6178, 0x75,
	0x6179, 0x75,
	0x617a, 0x75,
	0x617b, 0x75,
	0x617c, 0x75,
	0x617d, 0x75,
	0x617e, 0x75,
	0x617f, 0x75,
	0x6180, 0x75,
	0x6181, 0x75,
	0x6182, 0x75,
	0x6183, 0x75,
	0x6184, 0x75,
	0x6185, 0x75,
	0x6186, 0x75,
	0x6187, 0x75,
	0x6188, 0x75,
	0x6189, 0x75,
	0x618a, 0x75,
	0x618b, 0x75,
	0x618c, 0x75,
	0x618d, 0x75,
	0x618e, 0x75,
	0x618f, 0x75,
	0x6190, 0x75,
	0x6191, 0x75,
	0x6192, 0x75,
	0x6193, 0x75,
	0x6194, 0x75,
	0x6195, 0x75,
	0x6196, 0x75,
	0x6197, 0x75,
	0x6198, 0x75,
	0x6199, 0x75,
	0x619a, 0x75,
	0x619b, 0x75,
	0x619c, 0x75,
	0x619d, 0x75,
	0x619e, 0x75,
	0x619f, 0x75,
	0x61a0, 0x75,
	0x61a1, 0x75,
	0x61a2, 0x75,
	0x61a3, 0x75,
	0x61a4, 0x75,
	0x61a5, 0x75,
	0x61a6, 0x75,
	0x61a7, 0x75,
	0x61a8, 0x75,
	0x61a9, 0x75,
	0x61aa, 0x75,
	0x61ab, 0x75,
	0x61ac, 0x75,
	0x61ad, 0x75,
	0x61ae, 0x75,
	0x61af, 0x75,
	0x5d62, 0x07,
	0x5d40, 0x02,
	0x5d41, 0x01,
	0x5d63, 0x08,
	0x5d64, 0x01,
	0x5d65, 0xff,
	0x5d56, 0x00,
	0x5d57, 0x20,
	0x5d58, 0x00,
	0x5d59, 0x20,
	0x5d5a, 0x00,
	0x5d5b, 0x0c,
	0x5d5c, 0x02,
	0x5d5d, 0x40,
	0x5d5e, 0x02,
	0x5d5f, 0x40,
	0x5d60, 0x03,
	0x5d61, 0x40,
	0x5d4a, 0x02,
	0x5d4b, 0x40,
	0x5d4c, 0x02,
	0x5d4d, 0x40,
	0x5d4e, 0x02,
	0x5d4f, 0x40,
	0x5d50, 0x18,
	0x5d51, 0x80,
	0x5d52, 0x18,
	0x5d53, 0x80,
	0x5d54, 0x18,
	0x5d55, 0x80,
	0x5d46, 0x01,  //  20  slope exp threshold
	0x5d47, 0x1b,  //  00
	0x5d48, 0x01,  //  22
	0x5d49, 0x1f,  //  00
	0x5d42, 0x20,
	0x5d43, 0x00,
	0x5d44, 0x22,
	0x5d45, 0x00,
	0x4221, 0x03,
	0x380f, 0xc8,  //  ae	5e
	0x380c, 0x06,  //  04
	0x380d, 0xd8,  //  47
	0x384c, 0x03,  //  02
	0x384d, 0x48,  //  0d
	0x388c, 0x03,  //  02
	0x388d, 0x78,  //  2b
	0x3501, 0x01,
	0x3502, 0xc8,
	0x3541, 0x01,
	0x3542, 0xc8,
	0x35c1, 0x00,
	0x35c2, 0x01,
	0x420e, 0xba,  //  66 test row crc reference value
	0x420f, 0xa5,  //  5d
	0x4210, 0x44,  //  a8
	0x4211, 0x48,  //  55
	0x507a, 0x6b,  //  5f
	0x507b, 0x7f,  //  46

	//  fixed delay mode
	0x379e, 0xa0,
	0x379f, 0x00,
	0x37a0, 0x21,
	0x35c2, 0x00,

	0x4f00, 0x00,
	0x4f01, 0x00,
	0x4f02, 0x00,
	0x4f03, 0x2c,
	0x3200, 0x00,  // group0 base addr=0x00
	0x3201, 0x0b,  // group1 base addr=0x0b
};

uint32_t sy_ovx3c_pwl_setting_24bit[] = {
	// pwl setings
	0x5e00, 0x00,
	0x5e01, 0x09,
	0x5e02, 0x09,
	0x5e03, 0x0a,
	0x5e04, 0x0a,
	0x5e05, 0x0a,
	0x5e06, 0x0b,
	0x5e07, 0x0b,
	0x5e08, 0x0c,
	0x5e09, 0x0c,
	0x5e0a, 0x0d,
	0x5e0b, 0x0d,
	0x5e0c, 0x0e,
	0x5e0d, 0x0e,
	0x5e0e, 0x0f,
	0x5e0f, 0x0f,
	0x5e10, 0x10,
	0x5e11, 0x10,
	0x5e12, 0x11,
	0x5e13, 0x11,
	0x5e14, 0x12,
	0x5e15, 0x12,
	0x5e16, 0x12,
	0x5e17, 0x12,
	0x5e18, 0x13,
	0x5e19, 0x13,
	0x5e1a, 0x13,
	0x5e1b, 0x14,
	0x5e1c, 0x14,
	0x5e1d, 0x14,
	0x5e1e, 0x15,
	0x5e1f, 0x15,
	0x5e20, 0x15,
	0x5e21, 0x16,
	0x5e22, 0x00,
	0x5e23, 0x02,
	0x5e26, 0x00,
	0x5e27, 0xff,
	0x5e29, 0x01,
	0x5e2a, 0x00,
	0x5e2c, 0x01,
	0x5e2d, 0x00,
	0x5e2f, 0x01,
	0x5e30, 0x00,
	0x5e32, 0x00,
	0x5e33, 0x80,
	0x5e34, 0x00,
	0x5e35, 0x00,
	0x5e36, 0x80,
	0x5e37, 0x00,
	0x5e38, 0x00,
	0x5e39, 0x80,
	0x5e3a, 0x00,
	0x5e3b, 0x00,
	0x5e3c, 0x80,
	0x5e3d, 0x00,
	0x5e3e, 0x00,
	0x5e3f, 0x80,
	0x5e40, 0x00,
	0x5e41, 0x00,
	0x5e42, 0x80,
	0x5e43, 0x00,
	0x5e44, 0x00,
	0x5e45, 0x80,
	0x5e46, 0x00,
	0x5e47, 0x00,
	0x5e48, 0x80,
	0x5e49, 0x00,
	0x5e4a, 0x00,
	0x5e4b, 0x80,
	0x5e4c, 0x00,
	0x5e4d, 0x00,
	0x5e4e, 0x80,
	0x5e50, 0x00,
	0x5e51, 0x80,
	0x5e53, 0x00,
	0x5e54, 0x80,
	0x5e56, 0x00,
	0x5e57, 0x40,
	0x5e59, 0x00,
	0x5e5a, 0x40,
	0x5e5c, 0x00,
	0x5e5d, 0x40,
	0x5e5f, 0x00,
	0x5e60, 0x40,
	0x5e62, 0x00,
	0x5e63, 0x40,
	0x5e65, 0x00,
	0x5e66, 0x40,
	0x5e68, 0x00,
	0x5e69, 0x40,
	0x5e6b, 0x00,
	0x5e6c, 0x40,
	0x5e6e, 0x00,
	0x5e6f, 0x40,
	0x5e71, 0x00,
	0x5e72, 0x40,
	0x5e74, 0x00,
	0x5e75, 0x40,
	0x5e77, 0x00,
	0x5e78, 0x40,
	0x5e7a, 0x00,
	0x5e7b, 0x40,
	0x5e7d, 0x00,
	0x5e7e, 0x40,
	0x5e80, 0x00,
	0x5e81, 0x40,
	0x5e83, 0x00,
	0x5e84, 0x40,

	0x5f00, 0x02,
	0x5f01, 0x08,
	0x5f02, 0x09,
	0x5f03, 0x0a,
	0x5f04, 0x0b,
	0x5f05, 0x0c,
	0x5f06, 0x0c,
	0x5f07, 0x0c,
	0x5f08, 0x0c,
	0x5f09, 0x0c,
	0x5f0a, 0x0d,
	0x5f0b, 0x0d,
	0x5f0c, 0x0d,
	0x5f0d, 0x0d,
	0x5f0e, 0x0d,
	0x5f0f, 0x0e,
	0x5f10, 0x0e,
	0x5f11, 0x0e,
	0x5f12, 0x0e,
	0x5f13, 0x0f,
	0x5f14, 0x0f,
	0x5f15, 0x10,
	0x5f16, 0x11,
	0x5f17, 0x11,
	0x5f18, 0x12,
	0x5f19, 0x12,
	0x5f1a, 0x13,
	0x5f1b, 0x13,
	0x5f1c, 0x14,
	0x5f1d, 0x14,
	0x5f1e, 0x16,
	0x5f1f, 0x16,
	0x5f20, 0x16,
	0x5f21, 0x08,
	0x5f22, 0x00,
	0x5f23, 0x01,
	0x5f26, 0x02,
	0x5f27, 0x00,
	0x5f29, 0x02,
	0x5f2a, 0x00,
	0x5f2c, 0x02,
	0x5f2d, 0x00,
	0x5f2f, 0x02,
	0x5f30, 0x00,
	0x5f32, 0x02,
	0x5f33, 0x00,
	0x5f34, 0x00,
	0x5f35, 0x02,
	0x5f36, 0x00,
	0x5f37, 0x00,
	0x5f38, 0x02,
	0x5f39, 0x00,
	0x5f3a, 0x00,
	0x5f3b, 0x02,
	0x5f3c, 0x00,
	0x5f3d, 0x00,
	0x5f3e, 0x02,
	0x5f3f, 0x00,
	0x5f40, 0x00,
	0x5f41, 0x02,
	0x5f42, 0x00,
	0x5f43, 0x00,
	0x5f44, 0x02,
	0x5f45, 0x00,
	0x5f46, 0x00,
	0x5f47, 0x04,
	0x5f48, 0x00,
	0x5f49, 0x00,
	0x5f4a, 0x04,
	0x5f4b, 0x00,
	0x5f4c, 0x00,
	0x5f4d, 0x04,
	0x5f4e, 0x00,
	0x5f50, 0x04,
	0x5f51, 0x00,
	0x5f53, 0x04,
	0x5f54, 0x00,
	0x5f56, 0x04,
	0x5f57, 0x00,
	0x5f59, 0x04,
	0x5f5a, 0x00,
	0x5f5c, 0x04,
	0x5f5d, 0x00,
	0x5f5f, 0x08,
	0x5f60, 0x00,
	0x5f62, 0x08,
	0x5f63, 0x00,
	0x5f65, 0x08,
	0x5f66, 0x00,
	0x5f68, 0x08,
	0x5f69, 0x00,
	0x5f6b, 0x08,
	0x5f6c, 0x00,
	0x5f6e, 0x10,
	0x5f6f, 0x00,
	0x5f71, 0x10,
	0x5f72, 0x00,
	0x5f74, 0x10,
	0x5f75, 0x00,
	0x5f77, 0x10,
	0x5f78, 0x00,
	0x5f7a, 0x20,
	0x5f7b, 0x00,
	0x5f7d, 0x20,
	0x5f7e, 0x00,
	0x5f80, 0x20,
	0x5f81, 0x00,
	0x5f83, 0x00,
	0x5f84, 0xff,


};
uint32_t sy_ovx3c_pwl_setting[] = {
	// pwl setings
	0x5E00, 0x00,
	0x5E01, 0x08,
	0x5E02, 0x08,
	0x5E03, 0x08,
	0x5E04, 0x08,
	0x5E05, 0x09,
	0x5E06, 0x09,
	0x5E07, 0x09,
	0x5E08, 0x09,
	0x5E09, 0x0a,
	0x5E0A, 0x0a,
	0x5E0B, 0x0a,
	0x5E0C, 0x0b,
	0x5E0D, 0x0b,
	0x5E0E, 0x0b,
	0x5E0F, 0x0c,
	0x5E10, 0x0d,
	0x5E11, 0x0d,
	0x5E12, 0x0d,
	0x5E13, 0x0d,
	0x5E14, 0x0e,
	0x5E15, 0x0e,
	0x5E16, 0x0e,
	0x5E17, 0x0e,
	0x5E18, 0x0e,
	0x5E19, 0x0f,
	0x5E1A, 0x0f,
	0x5E1B, 0x10,
	0x5E1C, 0x10,
	0x5E1D, 0x10,
	0x5E1E, 0x11,
	0x5E1F, 0x11,
	0x5E20, 0x11,
	0x5E21, 0x12,
	0x5E22, 0x00,
	0x5E23, 0x01,
	0x5E24, 0x00,
	0x5E25, 0x00,
	0x5E26, 0x00,
	0x5E27, 0x3f,
	0x5E28, 0x00,
	0x5E29, 0x00,
	0x5E2A, 0x40,
	0x5E2B, 0x00,
	0x5E2C, 0x00,
	0x5E2D, 0x40,
	0x5E2E, 0x00,
	0x5E2F, 0x00,
	0x5E30, 0x40,
	0x5E31, 0x00,
	0x5E32, 0x00,
	0x5E33, 0x40,
	0x5E34, 0x00,
	0x5E35, 0x00,
	0x5E36, 0x40,
	0x5E37, 0x00,
	0x5E38, 0x00,
	0x5E39, 0x40,
	0x5E3A, 0x00,
	0x5E3B, 0x00,
	0x5E3C, 0x40,
	0x5E3D, 0x00,
	0x5E3E, 0x00,
	0x5E3F, 0x40,
	0x5E40, 0x00,
	0x5E41, 0x00,
	0x5E42, 0x40,
	0x5E43, 0x00,
	0x5E44, 0x00,
	0x5E45, 0x40,
	0x5E46, 0x00,
	0x5E47, 0x00,
	0x5E48, 0x40,
	0x5E49, 0x00,
	0x5E4A, 0x00,
	0x5E4B, 0x40,
	0x5E4C, 0x00,
	0x5E4D, 0x00,
	0x5E4E, 0x40,
	0x5E4F, 0x00,
	0x5E50, 0x00,
	0x5E51, 0x40,
	0x5E52, 0x00,
	0x5E53, 0x00,
	0x5E54, 0x40,
	0x5E55, 0x00,
	0x5E56, 0x00,
	0x5E57, 0x40,
	0x5E58, 0x00,
	0x5E59, 0x00,
	0x5E5A, 0x80,
	0x5E5B, 0x00,
	0x5E5C, 0x00,
	0x5E5D, 0x80,
	0x5E5E, 0x00,
	0x5E5F, 0x01,
	0x5E60, 0x00,
	0x5E61, 0x00,
	0x5E62, 0x01,
	0x5E63, 0x00,
	0x5E64, 0x00,
	0x5E65, 0x01,
	0x5E66, 0x00,
	0x5E67, 0x00,
	0x5E68, 0x01,
	0x5E69, 0x00,
	0x5E6A, 0x00,
	0x5E6B, 0x01,
	0x5E6C, 0x00,
	0x5E6D, 0x00,
	0x5E6E, 0x01,
	0x5E6F, 0x00,
	0x5E70, 0x00,
	0x5E71, 0x01,
	0x5E72, 0x00,
	0x5E73, 0x00,
	0x5E74, 0x00,
	0x5E75, 0x80,
	0x5E76, 0x00,
	0x5E77, 0x00,
	0x5E78, 0x80,
	0x5E79, 0x00,
	0x5E7A, 0x00,
	0x5E7B, 0x80,
	0x5E7C, 0x00,
	0x5E7D, 0x00,
	0x5E7E, 0x80,
	0x5E7F, 0x00,
	0x5E80, 0x00,
	0x5E81, 0x80,
	0x5E82, 0x00,
	0x5E83, 0x00,
	0x5E84, 0x40,

	0x5f00, 0x02,
	0x5f01, 0x08,
	0x5f02, 0x09,
	0x5f03, 0x0a,
	0x5f04, 0x0b,
	0x5f05, 0x0c,
	0x5f06, 0x0c,
	0x5f07, 0x0c,
	0x5f08, 0x0c,
	0x5f09, 0x0c,
	0x5f0a, 0x0d,
	0x5f0b, 0x0d,
	0x5f0c, 0x0d,
	0x5f0d, 0x0d,
	0x5f0e, 0x0d,
	0x5f0f, 0x0e,
	0x5f10, 0x0e,
	0x5f11, 0x0e,
	0x5f12, 0x0e,
	0x5f13, 0x0f,
	0x5f14, 0x0f,
	0x5f15, 0x10,
	0x5f16, 0x11,
	0x5f17, 0x11,
	0x5f18, 0x12,
	0x5f19, 0x12,
	0x5f1a, 0x13,
	0x5f1b, 0x13,
	0x5f1c, 0x14,
	0x5f1d, 0x14,
	0x5f1e, 0x16,
	0x5f1f, 0x16,
	0x5f20, 0x16,
	0x5f21, 0x08,
	0x5f22, 0x00,
	0x5f23, 0x01,
	0x5f24, 0x00,
	0x5f25, 0x00,
	0x5f26, 0x02,
	0x5f27, 0x00,
	0x5f28, 0x00,
	0x5f29, 0x02,
	0x5f2a, 0x00,
	0x5f2b, 0x00,
	0x5f2c, 0x02,
	0x5f2d, 0x00,
	0x5f2e, 0x00,
	0x5f2f, 0x02,
	0x5f30, 0x00,
	0x5f31, 0x00,
	0x5f32, 0x02,
	0x5f33, 0x00,
	0x5f34, 0x00,
	0x5f35, 0x02,
	0x5f36, 0x00,
	0x5f37, 0x00,
	0x5f38, 0x02,
	0x5f39, 0x00,
	0x5f3a, 0x00,
	0x5f3b, 0x02,
	0x5f3c, 0x00,
	0x5f3d, 0x00,
	0x5f3e, 0x02,
	0x5f3f, 0x00,
	0x5f40, 0x00,
	0x5f41, 0x02,
	0x5f42, 0x00,
	0x5f43, 0x00,
	0x5f44, 0x02,
	0x5f45, 0x00,
	0x5f46, 0x00,
	0x5f47, 0x04,
	0x5f48, 0x00,
	0x5f49, 0x00,
	0x5f4a, 0x04,
	0x5f4b, 0x00,
	0x5f4c, 0x00,
	0x5f4d, 0x04,
	0x5f4e, 0x00,
	0x5f4f, 0x00,
	0x5f50, 0x04,
	0x5f51, 0x00,
	0x5f52, 0x00,
	0x5f53, 0x04,
	0x5f54, 0x00,
	0x5f55, 0x00,
	0x5f56, 0x04,
	0x5f57, 0x00,
	0x5f58, 0x00,
	0x5f59, 0x04,
	0x5f5a, 0x00,
	0x5f5b, 0x00,
	0x5f5c, 0x04,
	0x5f5d, 0x00,
	0x5f5e, 0x00,
	0x5f5f, 0x08,
	0x5f60, 0x00,
	0x5f61, 0x00,
	0x5f62, 0x08,
	0x5f63, 0x00,
	0x5f64, 0x00,
	0x5f65, 0x08,
	0x5f66, 0x00,
	0x5f67, 0x00,
	0x5f68, 0x08,
	0x5f69, 0x00,
	0x5f6a, 0x00,
	0x5f6b, 0x08,
	0x5f6c, 0x00,
	0x5f6d, 0x00,
	0x5f6e, 0x10,
	0x5f6f, 0x00,
	0x5f70, 0x00,
	0x5f71, 0x10,
	0x5f72, 0x00,
	0x5f73, 0x00,
	0x5f74, 0x10,
	0x5f75, 0x00,
	0x5f76, 0x00,
	0x5f77, 0x10,
	0x5f78, 0x00,
	0x5f79, 0x00,
	0x5f7a, 0x20,
	0x5f7b, 0x00,
	0x5f7c, 0x00,
	0x5f7d, 0x20,
	0x5f7e, 0x00,
	0x5f7f, 0x00,
	0x5f80, 0x20,
	0x5f81, 0x00,
	0x5f82, 0x00,
	0x5f83, 0x00,
	0x5f84, 0xff,
};

uint32_t of_ovx3c_pwl_setting[] = {
	0x5E00, 0x00,
	0x5E01, 0x08,
	0x5E02, 0x08,
	0x5E03, 0x08,
	0x5E04, 0x08,
	0x5E05, 0x09,
	0x5E06, 0x09,
	0x5E07, 0x09,
	0x5E08, 0x09,
	0x5E09, 0x0A,
	0x5E0A, 0x0A,
	0x5E0B, 0x0A,
	0x5E0C, 0x0B,
	0x5E0D, 0x0B,
	0x5E0E, 0x0B,
	0x5E0F, 0x0C,
	0x5E10, 0x0C,
	0x5E11, 0x0C,
	0x5E12, 0x0D,
	0x5E13, 0x0D,
	0x5E14, 0x0D,
	0x5E15, 0x0E,
	0x5E16, 0x0E,
	0x5E17, 0x0E,
	0x5E18, 0x0F,
	0x5E19, 0x0F,
	0x5E1A, 0x0F,
	0x5E1B, 0x10,
	0x5E1C, 0x10,
	0x5E1D, 0x10,
	0x5E1E, 0x11,
	0x5E1F, 0x11,    // 12
	0x5E20, 0x11,    // 12
	0x5E21, 0x12,    // 18
	0x5E22, 0x00,
	0x5E23, 0x01,
	0x5E24, 0x00,
	0x5E25, 0x00,
	0x5E26, 0x00,
	0x5E27, 0xFF,
	0x5E28, 0x00,
	0x5E29, 0x01,
	0x5E2A, 0x00,
	0x5E2B, 0x00,
	0x5E2C, 0x01,
	0x5E2D, 0x00,
	0x5E2E, 0x00,
	0x5E2F, 0x01,
	0x5E30, 0x00,
	0x5E31, 0x00,
	0x5E32, 0x01,
	0x5E33, 0x00,
	0x5E34, 0x00,
	0x5E35, 0x01,
	0x5E36, 0x00,
	0x5E37, 0x00,
	0x5E38, 0x01,
	0x5E39, 0x00,
	0x5E3A, 0x00,
	0x5E3B, 0x00,
	0x5E3C, 0x80,
	0x5E3D, 0x00,
	0x5E3E, 0x00,
	0x5E3F, 0x80,
	0x5E40, 0x00,
	0x5E41, 0x00,
	0x5E42, 0x80,
	0x5E43, 0x00,
	0x5E44, 0x00,
	0x5E45, 0x80,
	0x5E46, 0x00,
	0x5E47, 0x00,
	0x5E48, 0x80,
	0x5E49, 0x00,
	0x5E4A, 0x00,
	0x5E4B, 0x80,
	0x5E4C, 0x00,
	0x5E4D, 0x00,
	0x5E4E, 0x80,
	0x5E4F, 0x00,
	0x5E50, 0x00,
	0x5E51, 0x80,
	0x5E52, 0x00,
	0x5E53, 0x00,
	0x5E54, 0x80,
	0x5E55, 0x00,
	0x5E56, 0x00,
	0x5E57, 0x40,
	0x5E58, 0x00,
	0x5E59, 0x00,
	0x5E5A, 0x40,
	0x5E5B, 0x00,
	0x5E5C, 0x00,
	0x5E5D, 0x40,
	0x5E5E, 0x00,
	0x5E5F, 0x00,
	0x5E60, 0x40,
	0x5E61, 0x00,
	0x5E62, 0x00,
	0x5E63, 0x40,
	0x5E64, 0x00,
	0x5E65, 0x00,
	0x5E66, 0x40,
	0x5E67, 0x00,
	0x5E68, 0x00,
	0x5E69, 0x40,
	0x5E6A, 0x00,
	0x5E6B, 0x00,
	0x5E6C, 0x40,
	0x5E6D, 0x00,
	0x5E6E, 0x00,
	0x5E6F, 0x40,
	0x5E70, 0x00,
	0x5E71, 0x00,
	0x5E72, 0x40,
	0x5E73, 0x00,
	0x5E74, 0x00,
	0x5E75, 0x40,
	0x5E76, 0x00,
	0x5E77, 0x00,
	0x5E78, 0x40,
	0x5E79, 0x00,
	0x5E7A, 0x00,
	0x5E7B, 0x20,    // 40
	0x5E7C, 0x00,
	0x5E7D, 0x00,
	0x5E7E, 0x20,
	0x5E7F, 0x00,
	0x5E80, 0x00,
	0x5E81, 0x20,
	0x5E82, 0x00,
	0x5E83, 0x00,
	0x5E84, 0x20,    // 00

	0x5f00, 0x02,
	0x5f01, 0x08,
	0x5f02, 0x09,
	0x5f03, 0x0a,
	0x5f04, 0x0b,
	0x5f05, 0x0c,
	0x5f06, 0x0c,
	0x5f07, 0x0c,
	0x5f08, 0x0c,
	0x5f09, 0x0c,
	0x5f0a, 0x0d,
	0x5f0b, 0x0d,
	0x5f0c, 0x0d,
	0x5f0d, 0x0d,
	0x5f0e, 0x0d,
	0x5f0f, 0x0e,
	0x5f10, 0x0e,
	0x5f11, 0x0e,
	0x5f12, 0x0e,
	0x5f13, 0x0f,
	0x5f14, 0x0f,
	0x5f15, 0x10,
	0x5f16, 0x11,
	0x5f17, 0x11,
	0x5f18, 0x12,
	0x5f19, 0x12,
	0x5f1a, 0x13,
	0x5f1b, 0x13,
	0x5f1c, 0x14,
	0x5f1d, 0x14,
	0x5f1e, 0x16,
	0x5f1f, 0x16,
	0x5f20, 0x16,
	0x5f21, 0x08,
	0x5f22, 0x00,
	0x5f23, 0x01,
	0x5f26, 0x02,
	0x5f27, 0x00,
	0x5f29, 0x02,
	0x5f2a, 0x00,
	0x5f2c, 0x02,
	0x5f2d, 0x00,
	0x5f2f, 0x02,
	0x5f30, 0x00,
	0x5f32, 0x02,
	0x5f33, 0x00,
	0x5f34, 0x00,
	0x5f35, 0x02,
	0x5f36, 0x00,
	0x5f37, 0x00,
	0x5f38, 0x02,
	0x5f39, 0x00,
	0x5f3a, 0x00,
	0x5f3b, 0x02,
	0x5f3c, 0x00,
	0x5f3d, 0x00,
	0x5f3e, 0x02,
	0x5f3f, 0x00,
	0x5f40, 0x00,
	0x5f41, 0x02,
	0x5f42, 0x00,
	0x5f43, 0x00,
	0x5f44, 0x02,
	0x5f45, 0x00,
	0x5f46, 0x00,
	0x5f47, 0x04,
	0x5f48, 0x00,
	0x5f49, 0x00,
	0x5f4a, 0x04,
	0x5f4b, 0x00,
	0x5f4c, 0x00,
	0x5f4d, 0x04,
	0x5f4e, 0x00,
	0x5f50, 0x04,
	0x5f51, 0x00,
	0x5f53, 0x04,
	0x5f54, 0x00,
	0x5f56, 0x04,
	0x5f57, 0x00,
	0x5f59, 0x04,
	0x5f5a, 0x00,
	0x5f5c, 0x04,
	0x5f5d, 0x00,
	0x5f5f, 0x08,
	0x5f60, 0x00,
	0x5f62, 0x08,
	0x5f63, 0x00,
	0x5f65, 0x08,
	0x5f66, 0x00,
	0x5f68, 0x08,
	0x5f69, 0x00,
	0x5f6b, 0x08,
	0x5f6c, 0x00,
	0x5f6e, 0x10,
	0x5f6f, 0x00,
	0x5f71, 0x10,
	0x5f72, 0x00,
	0x5f74, 0x10,
	0x5f75, 0x00,
	0x5f77, 0x10,
	0x5f78, 0x00,
	0x5f7a, 0x20,
	0x5f7b, 0x00,
	0x5f7d, 0x20,
	0x5f7e, 0x00,
	0x5f80, 0x20,
	0x5f81, 0x00,
	0x5f83, 0x00,
	0x5f84, 0xff,
};

uint32_t ovx3c_width_1920_init_setting[] = {
	/****1920*xxxx***/
	0x3800, 0x00,  // X_ADDR_START
	0x3801, 0x00,
	0x3808, 0x07,  // X_OUTPUT_SIZE
	0x3809, 0x80,
};

uint32_t ovx3c_height_1080_init_setting[] = {
	/****xxxx*1080****/
	0x3802, 0x00,  // Y_ADDR_START
	0x3803, 0x08,
	0x380A, 0x04,  // Y_OUTPUT_SIZE
	0x380B, 0x38,
};

uint32_t ovx3c_res_1280x720_init_setting[] = {
	0x3802, 0x01,
	0x3803, 0x1C,
	0x3806, 0x03,
	0x3807, 0xF3,
	0x3808, 0x05,
	0x3809, 0x00,
	0x380a, 0x02,
	0x380b, 0xD0,
	0x3810, 0x01,
	0x3811, 0x48,
	0x3812, 0x00,
	0x3813, 0x04,
	0x4603, 0x13,  // VFIFO Manual start mode
	0x4610, 0x00,  // vfifo h0_start_h
	0x4611, 0x40,  // vfifo h0_start_l
	0x4614, 0x00,  // vfifo h1_start_h
	0x4615, 0x40,  // vfifo h1_start_l
};

uint32_t ovx3c_trigger_arbitrary_mode_setting[] = {
    //  FSIN Settings
	0x3015, 0x0A,  // GPIO setting to receive GSIN pulse
	0x3009, 0x02,  // GPIO setting to receive GSIN pulse
	0x3822, 0x24,  // enable mode fix timing counter, numb of rows before frame end
	0x3823, 0x50,  // ext_vsync_en, enable set row counter manually
	0x383e, 0x81,  // vsync_ext_rst_dis
	0x3881, 0x34,  // hdr_num, ext_vsync_adj_en
	0x3882, 0x02,  // number of rows before frame end
	0x3883, 0x9E,  // VTS - (3826, 3827), VTS = 0x02DF
	0x388e, 0x01,  //
	0x388f, 0x00,  //
	0x3892, 0x44,  //  enable cs adjustment
	0x3836, 0x00,
	0x3837, 0x02,
	0x3826, 0x00,  // tc_r_init_man = VTS - max(DCG, S-VS-2) - 3
	0x3827, 0x41,
};

uint32_t ovx3c_again_lut[] = {
	0x80,
	0x82,
	0x85,
	0x88,
	0x8b,
	0x8e,
	0x91,
	0x94,
	0x98,
	0x9b,
	0x9e,
	0xa2,
	0xa5,
	0xa9,
	0xad,
	0xb1,
	0xb5,
	0xb8,
	0xbd,
	0xc1,
	0xc5,
	0xc9,
	0xce,
	0xd2,
	0xd7,
	0xdb,
	0xe0,
	0xe5,
	0xea,
	0xef,
	0xf5,
	0xfa,
	0x100,
	0x105,
	0x10b,
	0x111,
	0x117,
	0x11d,
	0x123,
	0x129,
	0x130,
	0x137,
	0x13d,
	0x144,
	0x14b,
	0x153,
	0x15a,
	0x162,
	0x16a,
	0x171,
	0x17a,
	0x182,
	0x18a,
	0x193,
	0x19c,
	0x1a5,
	0x1ae,
	0x1b7,
	0x1c1,
	0x1cb,
	0x1d5,
	0x1df,
	0x1ea,
	0x1f5,
	0x200,
	0x20b,
	0x216,
	0x222,
	0x22e,
	0x23a,
	0x247,
	0x253,
	0x260,
	0x26e,
	0x27b,
	0x289,
	0x297,
	0x2a6,
	0x2b5,
	0x2c4,
	0x2d4,
	0x2e3,
	0x2f4,
	0x304,
	0x315,
	0x326,
	0x338,
	0x34a,
	0x35d,
	0x36f,
	0x383,
	0x396,
	0x3ab,
	0x3bf,
	0x3d4,
	0x3ea,
	0x400,
	0x416,
	0x42d,
	0x444,
	0x45c,
	0x475,
	0x48e,
	0x4a7,
	0x4c1,
	0x4dc,
	0x4f7,
	0x513,
	0x52f,
	0x54d,
	0x56a,
	0x589,
	0x5a8,
	0x5c7,
	0x5e8,
	0x609,
	0x62b,
	0x64d,
	0x671,
	0x695,
	0x6ba,
	0x6df,
	0x706,
	0x72d,
	0x756,
	0x77f,
	0x7a9,
	0x7d4,
	0x7fe,
};

uint32_t ovx3c_dgain_lut[] = {
	0x200,
	0x20b,
	0x216,
	0x222,
	0x22e,
	0x23a,
	0x247,
	0x253,
	0x260,
	0x26e,
	0x27b,
	0x289,
	0x297,
	0x2a6,
	0x2b5,
	0x2c4,
	0x2d4,
	0x2e3,
	0x2f4,
	0x304,
	0x315,
	0x326,
	0x338,
	0x34a,
	0x35d,
	0x36f,
	0x383,
	0x396,
	0x3ab,
	0x3bf,
	0x3d4,
	0x3ea,
	0x400,
	0x416,
	0x42d,
	0x444,
	0x45c,
	0x475,
	0x48e,
	0x4a7,
	0x4c1,
	0x4dc,
	0x4f7,
	0x513,
	0x52f,
	0x54d,
	0x56a,
	0x589,
	0x5a8,
	0x5c7,
	0x5e8,
	0x609,
	0x62b,
	0x64d,
	0x671,
	0x695,
	0x6ba,
	0x6df,
	0x706,
	0x72d,
	0x756,
	0x77f,
	0x7a9,
	0x7d4,
	0x7ff,
};

uint32_t ovx3c_x3_30fps_linear_init_setting[] = {
};

static uint32_t max9296_stream_on_setting[] = {
	0x0313, 0x62,
};

static uint32_t max9296_stream_off_setting[] = {
	0x0313, 0x00,
};

static uint32_t max96712_stream_on_setting[] = {
	0x08A0, 0x84,  	// MIPI output enable
};

static uint32_t max96712_stream_off_setting[] = {
	0x08A0, 0x00,  	// MIPI output enable
};

static uint8_t sunny_max96718_1p249Gbps_setting[] = {
	// max96718 output: 1.249Gbps/lane
	// dphy2 ---- portB
	0x04, 0x90, 0x1E, 0x00, 0xf4,
	// 0x00, 0xf0,
	0x04, 0x90, 0x1E, 0x03, 0x92,
	0x04, 0x90, 0x1E, 0x07, 0x04,
	0x04, 0x90, 0x1E, 0x08, 0x31,
	0x04, 0x90, 0x1E, 0x0A, 0x91,
	0x04, 0x90, 0x03, 0x21, 0x5C,
	0x04, 0x90, 0x03, 0x22, 0x07,
	0x04, 0x90, 0x03, 0x23, 0x00,
	0x04, 0x90, 0x1E, 0x00, 0xf5,
	0x00, 0x64,

	// dphy1 ---- portA
	0x04, 0x90, 0x1D, 0x00, 0xf4,
	// 0x00, 0xf0,
	0x04, 0x90, 0x1D, 0x03, 0x92,
	0x04, 0x90, 0x1D, 0x07, 0x04,
	0x04, 0x90, 0x1D, 0x08, 0x31,
	0x04, 0x90, 0x1D, 0x0A, 0x91,
	0x04, 0x90, 0x03, 0x1E, 0x5C,
	0x04, 0x90, 0x03, 0x1F, 0x07,
	0x04, 0x90, 0x03, 0x20, 0x00,
	0x04, 0x90, 0x1D, 0x00, 0xf5,
	0x00, 0x64,
};

#endif  // UTILITY_SENSOR_INC_OVX3C_SETTING_H_
